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linux-rolling-lts
linux-rolling-stable
master
Linux kernel stable tree (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
gpu
/
drm
/
i915
/
intel_dpll_mgr.c
Age
Commit message (
Expand
)
Author
Files
Lines
2018-07-18
Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/dr...
Dave Airlie
1
-24
/
+85
2018-07-05
drm/i915: Mark expected switch fall-throughs
Gustavo A. R. Silva
1
-0
/
+3
2018-07-02
drm/i915: Use drm_plane_mask() & co.
Ville Syrjälä
1
-3
/
+3
2018-06-21
drm/i915/icl: Do read-modify-write as needed during MG PLL programming
Imre Deak
1
-4
/
+35
2018-06-21
drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
Imre Deak
1
-20
/
+47
2018-06-15
drm/i915/icl: start adding the TBT pll
Paulo Zanoni
1
-4
/
+16
2018-06-02
drm/i915/icl: Get DDI clock for ICL based on PLLs.
Manasi Navare
1
-0
/
+70
2018-05-08
drm/i915/icl: compute the MG PLL registers
Paulo Zanoni
1
-1
/
+222
2018-05-08
drm/i915/icl: compute the combo PHY (DPLL) DP registers
Paulo Zanoni
1
-1
/
+86
2018-05-08
drm/i915/icl: compute the combo PHY (DPLL) HDMI registers
Paulo Zanoni
1
-3
/
+36
2018-05-08
drm/i915/icl: add basic support for the ICL clocks
Paulo Zanoni
1
-1
/
+312
2018-03-27
drm/i915: reorder dpll_info members
Lucas De Marchi
1
-24
/
+24
2018-03-27
drm/i915: use flags from dpll_info embedded in intel_shared_dpll
Lucas De Marchi
1
-2
/
+0
2018-03-27
drm/i915: use id from intel_shared_dpll.info
Lucas De Marchi
1
-71
/
+89
2018-03-27
drm/i915: use name from intel_shared_dpll.info
Lucas De Marchi
1
-12
/
+14
2018-03-27
drm/i915: use funcs from intel_shared_dpll.info
Lucas De Marchi
1
-5
/
+4
2018-03-27
drm/i915: add dpll_info inside intel_shared_dpll
Lucas De Marchi
1
-0
/
+1
2018-03-27
drm/i915: move dpll_info to header
Lucas De Marchi
1
-7
/
+0
2017-11-16
drm/i915/cnl: Simplify dco_fraction calculation.
Rodrigo Vivi
1
-3
/
+6
2017-11-16
drm/i915/cnl: Don't blindly replace qdiv.
Rodrigo Vivi
1
-2
/
+1
2017-11-16
drm/i915/cnl: Fix wrpll math for higher freqs.
Rodrigo Vivi
1
-3
/
+3
2017-11-16
drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
Rodrigo Vivi
1
-18
/
+12
2017-11-16
drm/i915/cnl: Remove useless conversion.
Rodrigo Vivi
1
-3
/
+3
2017-11-16
drm/i915/cnl: Remove spurious central_freq.
Rodrigo Vivi
1
-1
/
+0
2017-11-09
drm/i915: Replace dig_port->port with encoder port for BXT DPLL selection
Ville Syrjälä
1
-9
/
+1
2017-10-27
drm/i915: Start using output_types for DPLL selection
Ville Syrjälä
1
-23
/
+13
2017-10-25
drm/i915: Adjust system agent voltage on CNL if required by DDI ports
Ville Syrjälä
1
-8
/
+8
2017-10-17
drm/i915/cnl: Fix PLL initialization for HDMI.
Rodrigo Vivi
1
-1
/
+1
2017-08-11
drm/i915/cnl: Dump the right pll registers when dumping pipe config.
Rodrigo Vivi
1
-1
/
+10
2017-06-15
drm/i915/cnl: make function cnl_ddi_dp_set_dpll_hw_state static
Colin Ian King
1
-2
/
+3
2017-06-12
drm/i915/cnl: Enable wrpll computation for CNL
Kahola, Mika
1
-2
/
+138
2017-06-12
drm/i915/cnl: Initialize PLLs
Rodrigo Vivi
1
-2
/
+298
2017-02-10
drm/i915: Remove unused function intel_ddi_get_link_dpll()
Ander Conselvan de Oliveira
1
-44
/
+8
2017-02-03
drm/i915/bxt: Add MST support when do DPLL calculation
Lee, Shawn C
1
-1
/
+2
2017-01-24
drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.
Rodrigo Vivi
1
-1
/
+1
2017-01-02
drm/i915: Move intel_atomic_get_shared_dpll_state() to intel_dpll_mgr.c
Ander Conselvan de Oliveira
1
-0
/
+31
2016-12-30
drm/i915: Add dpll entrypoint for dumping hw state
Ander Conselvan de Oliveira
1
-0
/
+79
2016-12-30
drm/i915: Update kerneldoc for intel_dpll_mgr.c
Ander Conselvan de Oliveira
1
-5
/
+86
2016-12-30
drm/i915: Rename intel_shared_dpll->mode_set() to prepare()
Ander Conselvan de Oliveira
1
-4
/
+4
2016-12-30
drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state
Ander Conselvan de Oliveira
1
-36
/
+36
2016-12-30
drm/i915: Rename intel_shared_dpll_commit() to _swap_state()
Ander Conselvan de Oliveira
1
-1
/
+6
2016-12-30
drm/i915: Introduce intel_release_shared_dpll()
Ander Conselvan de Oliveira
1
-23
/
+18
2016-12-02
drm/i915/glk: Update Port PLL enable sequence for Geminilkae
Madhav Chauhan
1
-0
/
+20
2016-12-02
drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
Ander Conselvan de Oliveira
1
-0
/
+6
2016-12-02
drm/i915/glk: Implement Geminilake DDI init sequence
Ander Conselvan de Oliveira
1
-2
/
+2
2016-12-02
drm/i915/glk: Reuse broxton code for geminilake
Ander Conselvan de Oliveira
1
-1
/
+1
2016-11-17
drm/i915: Assorted INTEL_INFO(dev) cleanups
Tvrtko Ursulin
1
-3
/
+2
2016-10-28
drm/i915: Address broxton phy registers based on phy and channel number
Ander Conselvan de Oliveira
1
-38
/
+46
2016-10-14
drm/i915: Make IS_BROXTON only take dev_priv
Tvrtko Ursulin
1
-1
/
+1
2016-10-14
drm/i915: Make IS_KABYLAKE only take dev_priv
Tvrtko Ursulin
1
-1
/
+1
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