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path: root/drivers/gpu/drm/tegra/sor.c
AgeCommit message (Expand)AuthorFilesLines
2014-06-09drm/tegra: sor - Remove obsolete commentThierry Reding1-1/+1
2014-06-09drm/tegra: sor - Enable only the necessary number of lanesThierry Reding1-1/+1
2014-06-09drm/tegra: sor - Power on only the necessary lanesThierry Reding1-3/+17
2014-06-09drm/tegra: sor - Do not program interlaced mode registersThierry Reding1-3/+0
2014-06-09drm/tegra: sor - Do not hardcode link speedThierry Reding1-2/+2
2014-06-09drm/tegra: sor - Do not hardcode number of blank symbolsThierry Reding1-3/+23
2014-06-09drm/tegra: sor - Don't hardcode link parametersThierry Reding1-10/+213
2014-06-09drm/tegra: sor - Change power down orderingStéphane Marchesin1-1/+1
2014-06-09drm/tegra: sor - Fix copy/paste errorStéphane Marchesin1-1/+1
2014-06-09drm/tegra: sor - Remove pixel clock roundingStéphane Marchesin1-3/+0
2014-06-06drm/tegra: sor - Make debugfs setup consistentThierry Reding1-6/+5
2014-06-06drm/tegra: sor - Recursively remove debugfs treeThierry Reding1-1/+1
2014-06-06drm/tegra: Remove host1x drm_bus implementationThierry Reding1-3/+3
2014-06-06drm/tegra: sor - Protect CRC debugfs against enable stateThierry Reding1-24/+45
2014-06-06drm/tegra: dc - Compute shift clock divider in output driversThierry Reding1-4/+6
2014-06-06drm/tegra: sor - Add CRC debugfs supportThierry Reding1-0/+121
2014-04-04drm/tegra: Add eDP supportThierry Reding1-0/+1092