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path: root/drivers/phy/qualcomm/phy-qcom-qusb2.c
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2023-07-17phy: Explicitly include correct DT includesRob Herring1-1/+0
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: qcom-qusb2: add QUSB2 support for IPQ9574Varadarajan Narayanan1-0/+3
Add the phy init sequence for the Super Speed ports found on IPQ9574. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/7c67e9e92227add6544009092adbd400c3cb47db.1683630932.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-09-24phy: qcom-qusb2: Use dev_err_probe() to simplify codeYuan Can1-18/+9
In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can <yuancan@huawei.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20220922111228.36355-7-yuancan@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: qcom-qusb2: Add compatible for MSM8953Luca Weiss1-0/+3
Add compatible for MSM8953 QUSB2 device which reuses MSM8996 configuration. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220112194118.178026-3-luca@z3ntu.xyz Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-26phy: qcom-qusb2: Fix a memory leak on probeVladimir Zapolskiy1-6/+10
On success nvmem_cell_read() returns a pointer to a dynamically allocated buffer, and therefore it shall be freed after usage. The issue is reported by kmemleak: # cat /sys/kernel/debug/kmemleak unreferenced object 0xffff3b3803e4b280 (size 128): comm "kworker/u16:1", pid 107, jiffies 4294892861 (age 94.120s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<000000007739afdc>] __kmalloc+0x27c/0x41c [<0000000071c0fbf8>] nvmem_cell_read+0x40/0xe0 [<00000000e803ef1f>] qusb2_phy_init+0x258/0x5bc [<00000000fc81fcfa>] phy_init+0x70/0x110 [<00000000e3d48a57>] dwc3_core_soft_reset+0x4c/0x234 [<0000000027d1dbd4>] dwc3_core_init+0x68/0x990 [<000000001965faf9>] dwc3_probe+0x4f4/0x730 [<000000002f7617ca>] platform_probe+0x74/0xf0 [<00000000a2576cac>] really_probe+0xc4/0x470 [<00000000bc77f2c5>] __driver_probe_device+0x11c/0x190 [<00000000130db71f>] driver_probe_device+0x48/0x110 [<0000000019f36c2b>] __device_attach_driver+0xa4/0x140 [<00000000e5812ff7>] bus_for_each_drv+0x84/0xe0 [<00000000f4bac574>] __device_attach+0xe4/0x1c0 [<00000000d3beb631>] device_initial_probe+0x20/0x30 [<000000008019b9db>] bus_probe_device+0xa4/0xb0 Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210922233548.2150244-1-vladimir.zapolskiy@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-05phy: qcom-qusb2: Add missing vdd supplyShawn Guo1-1/+1
Per downstream kernel, beside vdda-pll and vdda-phy-dpdm, vdd is also a required supply for QUSB2 PHY digital circuit operation. The driver works right now likely because firmware already sets it up. Add it for correctness and completeness. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210928022002.26286-3-shawn.guo@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01phy: qcom-qusb2: Add compatible for QCM2290Shawn Guo1-0/+3
Add compatible for QCM2290 QUSB2 device which reuses SM6115 configuration. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210919031110.25064-3-shawn.guo@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-06-24phy: qcom-qusb2: Add configuration for SM4250 and SM6115Iskren Chernev1-0/+34
The SM4250 and SM6115 uses the same register layout as MSM8996, but the tune sequence is a bit different. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Link: https://lore.kernel.org/r/20210622203240.559979-4-iskren.chernev@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-02-04phy: qcom-qusb2: add QUSB2 support for IPQ6018Kathiravan T1-0/+44
Add the phy init sequence for the Super Speed ports found on IPQ6018. Signed-off-by: Kathiravan T <kathirav@codeaurora.org> [baruch: add ipq6018_regs_layout[], drop binding change] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/b8c22dddf1f70d89e135fe1ae705ddc68e295ebb.1611756920.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qusb2: Add configuration for SDM660AngeloGioacchino Del Regno1-0/+15
The SDM660 SoC uses the same configuration as MSM8996, but the clock scheme uses a differential reference clock and none of the SoCs in this series (630, 636 and others) have got a usable PHY_CLK_SCHEME register in the TCSR for clk scheme detection. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-2-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qusb2: Allow specifying default clock schemeAngeloGioacchino Del Regno1-2/+13
The TCSR's PHY_CLK_SCHEME register is not available on all SoC models, but some may still use a differential reference clock. In preparation for these SoCs, add a se_clk_scheme_default configuration entry and declare it to true for all currently supported SoCs (retaining the previous defaults. This patch brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-1-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qualcomm: convert to devm_platform_ioremap_resource(_byname)Chunfeng Yun1-3/+1
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-10-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: qcom-qusb2: Add ipq8074 device compatibleSivaprakash Murugesan1-0/+3
Add ipq8074 qusb2 device compatible for high speed usb support. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Tested-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Link: https://lore.kernel.org/r/1591625479-4483-5-git-send-email-sivaprak@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-04-27phy: qcom-qusb2: Re add "qcom,sdm845-qusb2-phy" compat stringJohn Stultz1-0/+7
This patch fixes a regression in 5.7-rc1+ In commit 8fe75cd4cddf ("phy: qcom-qusb2: Add generic QUSB2 V2 PHY support"), the change was made to add "qcom,qusb2-v2-phy" as a generic compat string. However the change also removed the "qcom,sdm845-qusb2-phy" compat string, which is documented in the binding and already in use. This patch re-adds the "qcom,sdm845-qusb2-phy" compat string which allows the driver to continue to work with existing dts entries such as found on the db845c. Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 8fe75cd4cddf ("phy: qcom-qusb2: Add generic QUSB2 V2 PHY support") Reported-by: YongQin Liu <yongqin.liu@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qusb2: Add new overriding tuning parameters in QUSB2 V2 PHYSandeep Maheswaram1-0/+51
Added support for overriding bias-ctrl-value,charge-ctrl-value and hsdisc-trim-value params for QUSB2 V2 PHY Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qusb2: Add support for overriding tuning parameters in QUSB2 V2 PHYSandeep Maheswaram1-32/+43
Added new structure for overriding tuning parameters in QUSB2 V2 PHY as the override params are increased due to usage of generic QUSB2 V2 phy table. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qusb2: Add generic QUSB2 V2 PHY supportSandeep Maheswaram1-9/+9
Add generic QUSB2 V2 PHY table so the respective phys can use the same table. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-03phy: qcom-qusb2: fix missing assignment of ret when calling clk_prepare_enableColin Ian King1-1/+1
The error return from the call to clk_prepare_enable is not being assigned to variable ret even though ret is being used to check if the call failed. Fix this by adding in the missing assignment. Addresses-Coverity: ("Logically dead code") Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: qcom-qusb2: get optional clock by devm_clk_get_optional()Chunfeng Yun1-8/+3
Use devm_clk_get_optional() to get optional clock Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-07phy: qcom-qusb2: Add QUSB2 PHY support for msm8998Jeffrey Hugo1-0/+40
MSM8998 contains one QUSB2 PHY which is very similar to the existing sdm845 support. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: core: rework phy_set_mode to accept phy mode and submodeGrygorii Strashko1-1/+2
Currently the attempt to add support for Ethernet interface mode PHY (MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and duplicate there values from phy_interface_t enum (or introduce more PHY callbacks) [1]. Both approaches are ineffective and would lead to fast bloating of enum phy_mode or struct phy_ops in the process of adding more PHYs for different subsystems which will make them unmaintainable. As discussed in [1] the solution could be to introduce dual level PHYs mode configuration - PHY mode and PHY submode. The PHY mode will define generic PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem specific interface mode. The last is usually already defined in corresponding subsystem headers (phy_interface_t for Ethernet, enum usb_device_speed for USB). This patch is cumulative change which refactors PHY framework code to support dual level PHYs mode configuration - PHY mode and PHY submode. It extends .set_mode() callback to support additional parameter "int submode" and converts all corresponding PHY drivers to support new .set_mode() callback declaration. The new extended PHY API int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) is introduced to support dual level PHYs mode configuration and existing phy_set_mode() API is converted to macros, so PHY framework consumers do not need to be changed (~21 matches). [1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-21phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845Manu Gautam1-0/+1
Tune1 register on sdm845 is used to update HSTX_TRIM with fused setting. Enable same by specifying update_tune1_with_efuse flag for sdm845, otherwise driver ends up programming tune2 register. Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845") Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-21phy: qcom-qusb2: Use HSTX_TRIM fused value as isManu Gautam1-9/+10
Fix HSTX_TRIM tuning logic which instead of using fused value as HSTX_TRIM, incorrectly performs bitwise OR operation with existing default value. Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-10phy: qcom-qusb2: Quiet -EPROBE_DEFER from qusb2_phy_probe()Douglas Anderson1-1/+3
The -EPROBE_DEFER virus demands special case code to avoid printing error messages when the error is only -EPROBE_DEFER. Spread the virus to a new host: qusb2_phy_probe(). Specifically handle when our regulators might not be ready yet. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-05-20phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845Manu Gautam1-8/+118
There are two QUSB2 PHYs present on sdm845. In order to improve eye diagram for both the PHYs some parameters need to be changed. Provide device tree properties to override these from board specific device tree files. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-05-20phy: qcom-qusb2: Fix crash if nvmem cell not specifiedManu Gautam1-0/+4
Driver currently crashes due to NULL pointer deference while updating PHY tune register if nvmem cell is NULL. Since, fused value for Tune1/2 register is optional, we'd rather bail out. Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Cc: stable <stable@vger.kernel.org> # 4.14+ Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08phy: add SPDX identifier to QMP and QUSB2 PHY driversManu Gautam1-9/+1
The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08phy: qcom-qusb2: Add support for runtime PMManu Gautam1-0/+176
Disable clocks and enable DP/DM wakeup interrupts when suspending PHY. Core driver should notify speed to PHY driver to enable appropriate DP/DM wakeup interrupts polarity in suspend state. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08phy: qcom-qusb2: Add support for QUSB2 V2 versionManu Gautam1-0/+64
Use register layout to add additional registers present on QUSB2 PHY V2 version for PHY initialization. Other than new registers on V2, following two register's offset and bit definitions are different: POWERDOWN control and PLL_STATUS. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08phy: qcom-qusb2: Add support for different register layoutsManu Gautam1-40/+109
New version of QUSB2 PHY has some registers offset changed. Add support to have register layout for a target and update the same in phy_configuration. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-08phy: qcom-qusb2: Power-on PHY before initializationManu Gautam1-32/+15
PHY must be powered on before turning ON clocks and attempting to initialize it. Driver is exposing separate init and power_on routines for this. Apparently USB dwc3 core driver performs power-on after init. Also, poweron and init for QUSB2 PHY need to be executed together always, hence remove poweron callback from phy_ops and explicitly perform this from init, similar changes needed for poweroff. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-01phy: Group vendor specific phy driversVivek Gautam1-0/+493
Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: David S. Miller <davem@davemloft.net> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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