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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J7200 SoC Family Main Domain peripherals
*
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x00 0x70000000 0x00 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x70000000 0x100000>;
atf-sram@0 {
reg = <0x00 0x20000>;
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01900000 0x00 0x100000>; /* GICR */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
main_gpio_intr: interrupt-controller0 {
compatible = "ti,sci-intr";
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <131>;
ti,interrupt-ranges = <8 392 56>;
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <199>;
main_navss_intr: interrupt-controller1 {
compatible = "ti,sci-intr";
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <213>;
ti,interrupt-ranges = <0 64 64>,
<64 448 64>,
<128 672 64>;
};
main_udmass_inta: msi-controller@33d00000 {
compatible = "ti,sci-inta";
reg = <0x00 0x33d00000 0x00 0x100000>;
interrupt-controller;
#interrupt-cells = <0>;
interrupt-parent = <&main_navss_intr>;
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <209>;
ti,interrupt-ranges = <0 0 256>;
};
secure_proxy_main: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x32c00000 0x00 0x100000>,
<0x00 0x32400000 0x00 0x100000>,
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x3c000000 0x00 0x400000>,
<0x00 0x38000000 0x00 0x400000>,
<0x00 0x31120000 0x00 0x100>,
<0x00 0x33000000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
ti,sci-dev-id = <211>;
msi-parent = <&main_udmass_inta>;
};
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
reg = <0x00 0x31150000 0x00 0x100>,
<0x00 0x34000000 0x00 0x100000>,
<0x00 0x35000000 0x00 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <212>;
ti,ringacc = <&main_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>, /* TX_HCHAN */
<0x10>; /* TX_UHCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>, /* RX_HCHAN */
<0x0c>; /* RX_UHCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x00 0x310d0000 0x00 0x400>;
reg-names = "cpts";
clocks = <&k3_clks 201 1>;
clock-names = "cpts";
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
};
};
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x11c000 0x00 0x2b4>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 2>;
clock-names = "fclk";
};
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 2>;
clock-names = "fclk";
};
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 2>;
clock-names = "fclk";
};
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 2>;
clock-names = "fclk";
};
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 2>;
clock-names = "fclk";
};
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 2>;
clock-names = "fclk";
};
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 2>;
clock-names = "fclk";
};
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 2>;
clock-names = "fclk";
};
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 2>;
clock-names = "fclk";
};
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 2>;
clock-names = "fclk";
};
};
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