path: root/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_
#define ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_

/*
 *****************************************
 *   DCORE0_EDMA0_QM
 *   (Prototype: QMAN)
 *****************************************
 */

/* DCORE0_EDMA0_QM_GLBL_CFG0 */
#define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
#define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
#define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
#define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14
#define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000

/* DCORE0_EDMA0_QM_GLBL_CFG1 */
#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20
#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25
#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000

/* DCORE0_EDMA0_QM_GLBL_CFG2 */
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000

/* DCORE0_EDMA0_QM_GLBL_ERR_CFG */
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000

/* DCORE0_EDMA0_QM_GLBL_ERR_CFG1 */
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2
#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4

/* DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN */
#define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF

/* DCORE0_EDMA0_QM_GLBL_AXCACHE */
#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF
#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000
#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20
#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000
#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24
#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000

/* DCORE0_EDMA0_QM_GLBL_STS0 */
#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF
#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0
#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00
#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000
#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20
#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000
#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25
#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000
#define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31
#define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000

/* DCORE0_EDMA0_QM_GLBL_STS1 */
#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1
#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1
#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2

/* DCORE0_EDMA0_QM_GLBL_ERR_STS */
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000

/* DCORE0_EDMA0_QM_GLBL_ERR_STS_4 */
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24
#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000

/* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN */
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000

/* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 */
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24
#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000

/* DCORE0_EDMA0_QM_GLBL_PROT */
#define DCORE0_EDMA0_QM_GLBL_PROT_PQF_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_PROT_PQF_MASK 0xF
#define DCORE0_EDMA0_QM_GLBL_PROT_CQF_SHIFT 4
#define DCORE0_EDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0
#define DCORE0_EDMA0_QM_GLBL_PROT_CP_SHIFT 9
#define DCORE0_EDMA0_QM_GLBL_PROT_CP_MASK 0x3E00
#define DCORE0_EDMA0_QM_GLBL_PROT_ERR_SHIFT 14
#define DCORE0_EDMA0_QM_GLBL_PROT_ERR_MASK 0x4000
#define DCORE0_EDMA0_QM_GLBL_PROT_ARB_SHIFT 15
#define DCORE0_EDMA0_QM_GLBL_PROT_ARB_MASK 0x8000
#define DCORE0_EDMA0_QM_GLBL_PROT_PQC_SHIFT 16
#define DCORE0_EDMA0_QM_GLBL_PROT_PQC_MASK 0x10000
#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17
#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000
#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18
#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000
#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19
#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000
#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20
#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000
#define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21
#define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000
#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22
#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000
#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23
#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000

/* DCORE0_EDMA0_QM_PQ_BASE_LO */
#define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQ_BASE_HI */
#define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQ_SIZE */
#define DCORE0_EDMA0_QM_PQ_SIZE_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_SIZE_VAL_MASK 0x1F

/* DCORE0_EDMA0_QM_PQ_PI */
#define DCORE0_EDMA0_QM_PQ_PI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQ_CI */
#define DCORE0_EDMA0_QM_PQ_CI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQ_CFG0 */
#define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1

/* DCORE0_EDMA0_QM_PQ_CFG1 */
#define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF
#define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16
#define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000

/* DCORE0_EDMA0_QM_PQ_STS0 */
#define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF
#define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8
#define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00
#define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16
#define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000

/* DCORE0_EDMA0_QM_PQ_STS1 */
#define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0
#define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1
#define DCORE0_EDMA0_QM_PQ_STS1_BUSY_SHIFT 1
#define DCORE0_EDMA0_QM_PQ_STS1_BUSY_MASK 0x2

/* DCORE0_EDMA0_QM_CQ_CFG0 */
#define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1
#define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1
#define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2
#define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2
#define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4

/* DCORE0_EDMA0_QM_CQ_STS0 */
#define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF
#define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8
#define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00
#define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16
#define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000

/* DCORE0_EDMA0_QM_CQ_CFG1 */
#define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF
#define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
#define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000

/* DCORE0_EDMA0_QM_CQ_STS1 */
#define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1
#define DCORE0_EDMA0_QM_CQ_STS1_BUSY_SHIFT 1
#define DCORE0_EDMA0_QM_CQ_STS1_BUSY_MASK 0x2

/* DCORE0_EDMA0_QM_CQ_PTR_LO_0 */
#define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_PTR_HI_0 */
#define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_TSIZE_0 */
#define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_CTL_0 */
#define DCORE0_EDMA0_QM_CQ_CTL_0_UP_SHIFT 28
#define DCORE0_EDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000

/* DCORE0_EDMA0_QM_CQ_PTR_LO_1 */
#define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_PTR_HI_1 */
#define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_TSIZE_1 */
#define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_CTL_1 */
#define DCORE0_EDMA0_QM_CQ_CTL_1_UP_SHIFT 28
#define DCORE0_EDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000

/* DCORE0_EDMA0_QM_CQ_PTR_LO_2 */
#define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_PTR_HI_2 */
#define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_TSIZE_2 */
#define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_CTL_2 */
#define DCORE0_EDMA0_QM_CQ_CTL_2_UP_SHIFT 28
#define DCORE0_EDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000

/* DCORE0_EDMA0_QM_CQ_PTR_LO_3 */
#define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_PTR_HI_3 */
#define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_TSIZE_3 */
#define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_CTL_3 */
#define DCORE0_EDMA0_QM_CQ_CTL_3_UP_SHIFT 28
#define DCORE0_EDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000

/* DCORE0_EDMA0_QM_CQ_PTR_LO_4 */
#define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_PTR_HI_4 */
#define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_TSIZE_4 */
#define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_CTL_4 */
#define DCORE0_EDMA0_QM_CQ_CTL_4_UP_SHIFT 28
#define DCORE0_EDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000

/* DCORE0_EDMA0_QM_CQ_TSIZE_STS */
#define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_PTR_LO_STS */
#define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_PTR_HI_STS */
#define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_IFIFO_STS */
#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7
#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4
#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10
#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8
#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100

/* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO */
#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI */
#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO */
#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI */
#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO */
#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI */
#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO */
#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI */
#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_FENCE0_RDATA */
#define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF

/* DCORE0_EDMA0_QM_CP_FENCE1_RDATA */
#define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF

/* DCORE0_EDMA0_QM_CP_FENCE2_RDATA */
#define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF

/* DCORE0_EDMA0_QM_CP_FENCE3_RDATA */
#define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF

/* DCORE0_EDMA0_QM_CP_FENCE0_CNT */
#define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF

/* DCORE0_EDMA0_QM_CP_FENCE1_CNT */
#define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF

/* DCORE0_EDMA0_QM_CP_FENCE2_CNT */
#define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF

/* DCORE0_EDMA0_QM_CP_FENCE3_CNT */
#define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF

/* DCORE0_EDMA0_QM_CP_BARRIER_CFG */
#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0
#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16
#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000

/* DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
#define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
#define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET */
#define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_CP_STS */
#define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
#define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF
#define DCORE0_EDMA0_QM_CP_STS_ERDY_SHIFT 8
#define DCORE0_EDMA0_QM_CP_STS_ERDY_MASK 0x100
#define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9
#define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200
#define DCORE0_EDMA0_QM_CP_STS_MRDY_SHIFT 10
#define DCORE0_EDMA0_QM_CP_STS_MRDY_MASK 0x400
#define DCORE0_EDMA0_QM_CP_STS_SW_STOP_SHIFT 11
#define DCORE0_EDMA0_QM_CP_STS_SW_STOP_MASK 0x800
#define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_SHIFT 12
#define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000
#define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14
#define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000
#define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16
#define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000
#define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_SHIFT 30
#define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000

/* DCORE0_EDMA0_QM_CP_CURRENT_INST_LO */
#define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_CURRENT_INST_HI */
#define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_PRED */
#define DCORE0_EDMA0_QM_CP_PRED_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_PRED_UPEN */
#define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_DBG_0 */
#define DCORE0_EDMA0_QM_CP_DBG_0_CS_SHIFT 0
#define DCORE0_EDMA0_QM_CP_DBG_0_CS_MASK 0x1F
#define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5
#define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20
#define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6
#define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40
#define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7
#define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80
#define DCORE0_EDMA0_QM_CP_DBG_0_STALL_SHIFT 8
#define DCORE0_EDMA0_QM_CP_DBG_0_STALL_MASK 0x100

/* DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED */
#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3
#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8
#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300

/* DCORE0_EDMA0_QM_CP_IN_DATA_LO */
#define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_IN_DATA_HI */
#define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQC_HBW_BASE_LO */
#define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQC_HBW_BASE_HI */
#define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQC_SIZE */
#define DCORE0_EDMA0_QM_PQC_SIZE_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQC_PI */
#define DCORE0_EDMA0_QM_PQC_PI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQC_LBW_WDATA */
#define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQC_LBW_BASE_LO */
#define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQC_LBW_BASE_HI */
#define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PQC_CFG */
#define DCORE0_EDMA0_QM_PQC_CFG_EN_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_CFG_EN_MASK 0x1
#define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_SHIFT 4
#define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_MASK 0x10

/* DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND */
#define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3

/* DCORE0_EDMA0_QM_ARB_MASK */
#define DCORE0_EDMA0_QM_ARB_MASK_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MASK_VAL_MASK 0xF

/* DCORE0_EDMA0_QM_ARB_CFG_0 */
#define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1
#define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4
#define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10
#define DCORE0_EDMA0_QM_ARB_CFG_0_EN_SHIFT 8
#define DCORE0_EDMA0_QM_ARB_CFG_0_EN_MASK 0x100
#define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9
#define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200

/* DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH */
#define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3

/* DCORE0_EDMA0_QM_ARB_WRR_WEIGHT */
#define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF

/* DCORE0_EDMA0_QM_ARB_CFG_1 */
#define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_MASK 0x1

/* DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED */
#define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F

/* DCORE0_EDMA0_QM_ARB_MST_CRED_INC */
#define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */
#define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
#define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN */
#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 */
#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT */
#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_SLV_ID */
#define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F

/* DCORE0_EDMA0_QM_ARB_MST_QUIET_PER */
#define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT */
#define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F

/* DCORE0_EDMA0_QM_ARB_BASE_LO */
#define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_BASE_HI */
#define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_STATE_STS */
#define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS */
#define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F

/* DCORE0_EDMA0_QM_ARB_MSG_STS */
#define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1
#define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1
#define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2

/* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */
#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3

/* DCORE0_EDMA0_QM_ARB_ERR_CAUSE */
#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1
#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1
#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2
#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2
#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4

/* DCORE0_EDMA0_QM_ARB_ERR_MSG_EN */
#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1
#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1
#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2
#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2
#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4

/* DCORE0_EDMA0_QM_ARB_ERR_STS_DRP */
#define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3

/* DCORE0_EDMA0_QM_ARB_MST_CRED_STS */
#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F
#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24
#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000

/* DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 */
#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F
#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24
#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000

/* DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG */
#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0
#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1
#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4
#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10

/* DCORE0_EDMA0_QM_ARC_CQ_CFG0 */
#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1
#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1
#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2
#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2
#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4

/* DCORE0_EDMA0_QM_ARC_CQ_CFG1 */
#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF
#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000

/* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO */
#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI */
#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_TSIZE */
#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_CTL */
#define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28
#define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000

/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS */
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100

/* DCORE0_EDMA0_QM_ARC_CQ_STS0 */
#define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF
#define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8
#define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00
#define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16
#define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000

/* DCORE0_EDMA0_QM_ARC_CQ_STS1 */
#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1
#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1
#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2

/* DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS */
#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS */
#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS */
#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI */
#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO */
#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */
#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */
#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI */
#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO */
#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI */
#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO */
#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ADDR_OVRD */
#define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_SHIFT 0
#define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF

/* DCORE0_EDMA0_QM_CQ_IFIFO_CI */
#define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI */
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CQ_CTL_CI */
#define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_CQ_CTL_CI */
#define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_CFG */
#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0
#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1
#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1
#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2

/* DCORE0_EDMA0_QM_CP_EXT_SWITCH */
#define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1

/* DCORE0_EDMA0_QM_CP_SWITCH_WD_SET */
#define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_CP_SWITCH_WD */
#define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO */
#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI */
#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI */
#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO */
#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE */
#define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */
#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */
#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_QM_BASE_ADDR_HI */
#define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_QM_BASE_ADDR_LO */
#define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND */
#define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0
#define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3

/* DCORE0_EDMA0_QM_PQC_STS_0 */
#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF
#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16
#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000

/* DCORE0_EDMA0_QM_PQC_STS_1 */
#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0
#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF
#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4
#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10
#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5
#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20

/* DCORE0_EDMA0_QM_SEI_STATUS */
#define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0
#define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1
#define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1
#define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2

/* DCORE0_EDMA0_QM_SEI_MASK */
#define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_SHIFT 0
#define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_MASK 0x1
#define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1
#define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2

/* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO */
#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI */
#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_GLBL_ERR_WDATA */
#define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_L2H_MASK_LO */
#define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20
#define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000

/* DCORE0_EDMA0_QM_L2H_MASK_HI */
#define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_L2H_CMPR_LO */
#define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20
#define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000

/* DCORE0_EDMA0_QM_L2H_CMPR_HI */
#define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_LOCAL_RANGE_BASE */
#define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE */
#define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF

/* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */
#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31
#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000

/* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */
#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000

/* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */
#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31
#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000

/* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */
#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000

/* DCORE0_EDMA0_QM_IND_GW_APB_CFG */
#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0
#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF
#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31
#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000

/* DCORE0_EDMA0_QM_IND_GW_APB_WDATA */
#define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_IND_GW_APB_RDATA */
#define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_IND_GW_APB_STATUS */
#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0
#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1
#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1
#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2

/* DCORE0_EDMA0_QM_PERF_CNT_FREE_LO */
#define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PERF_CNT_FREE_HI */
#define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO */
#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI */
#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0
#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_QM_PERF_CNT_CFG */
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31
#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000

#endif /* ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ */