path: root/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_EDMA0_QM_REGS_H_
#define ASIC_REG_DCORE0_EDMA0_QM_REGS_H_

/*
 *****************************************
 *   DCORE0_EDMA0_QM
 *   (Prototype: QMAN)
 *****************************************
 */

#define mmDCORE0_EDMA0_QM_GLBL_CFG0 0x41CA000

#define mmDCORE0_EDMA0_QM_GLBL_CFG1 0x41CA004

#define mmDCORE0_EDMA0_QM_GLBL_CFG2 0x41CA008

#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG 0x41CA00C

#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG1 0x41CA010

#define mmDCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x41CA014

#define mmDCORE0_EDMA0_QM_GLBL_AXCACHE 0x41CA018

#define mmDCORE0_EDMA0_QM_GLBL_STS0 0x41CA01C

#define mmDCORE0_EDMA0_QM_GLBL_STS1 0x41CA020

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_0 0x41CA024

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_1 0x41CA028

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_2 0x41CA02C

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_3 0x41CA030

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_4 0x41CA034

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_0 0x41CA038

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_1 0x41CA03C

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_2 0x41CA040

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_3 0x41CA044

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 0x41CA048

#define mmDCORE0_EDMA0_QM_GLBL_PROT 0x41CA04C

#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_0 0x41CA050

#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_1 0x41CA054

#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_2 0x41CA058

#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_3 0x41CA05C

#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_0 0x41CA060

#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_1 0x41CA064

#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_2 0x41CA068

#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_3 0x41CA06C

#define mmDCORE0_EDMA0_QM_PQ_SIZE_0 0x41CA070

#define mmDCORE0_EDMA0_QM_PQ_SIZE_1 0x41CA074

#define mmDCORE0_EDMA0_QM_PQ_SIZE_2 0x41CA078

#define mmDCORE0_EDMA0_QM_PQ_SIZE_3 0x41CA07C

#define mmDCORE0_EDMA0_QM_PQ_PI_0 0x41CA080

#define mmDCORE0_EDMA0_QM_PQ_PI_1 0x41CA084

#define mmDCORE0_EDMA0_QM_PQ_PI_2 0x41CA088

#define mmDCORE0_EDMA0_QM_PQ_PI_3 0x41CA08C

#define mmDCORE0_EDMA0_QM_PQ_CI_0 0x41CA090

#define mmDCORE0_EDMA0_QM_PQ_CI_1 0x41CA094

#define mmDCORE0_EDMA0_QM_PQ_CI_2 0x41CA098

#define mmDCORE0_EDMA0_QM_PQ_CI_3 0x41CA09C

#define mmDCORE0_EDMA0_QM_PQ_CFG0_0 0x41CA0A0

#define mmDCORE0_EDMA0_QM_PQ_CFG0_1 0x41CA0A4

#define mmDCORE0_EDMA0_QM_PQ_CFG0_2 0x41CA0A8

#define mmDCORE0_EDMA0_QM_PQ_CFG0_3 0x41CA0AC

#define mmDCORE0_EDMA0_QM_PQ_CFG1_0 0x41CA0B0

#define mmDCORE0_EDMA0_QM_PQ_CFG1_1 0x41CA0B4

#define mmDCORE0_EDMA0_QM_PQ_CFG1_2 0x41CA0B8

#define mmDCORE0_EDMA0_QM_PQ_CFG1_3 0x41CA0BC

#define mmDCORE0_EDMA0_QM_PQ_STS0_0 0x41CA0C0

#define mmDCORE0_EDMA0_QM_PQ_STS0_1 0x41CA0C4

#define mmDCORE0_EDMA0_QM_PQ_STS0_2 0x41CA0C8

#define mmDCORE0_EDMA0_QM_PQ_STS0_3 0x41CA0CC

#define mmDCORE0_EDMA0_QM_PQ_STS1_0 0x41CA0D0

#define mmDCORE0_EDMA0_QM_PQ_STS1_1 0x41CA0D4

#define mmDCORE0_EDMA0_QM_PQ_STS1_2 0x41CA0D8

#define mmDCORE0_EDMA0_QM_PQ_STS1_3 0x41CA0DC

#define mmDCORE0_EDMA0_QM_CQ_CFG0_0 0x41CA0E0

#define mmDCORE0_EDMA0_QM_CQ_CFG0_1 0x41CA0E4

#define mmDCORE0_EDMA0_QM_CQ_CFG0_2 0x41CA0E8

#define mmDCORE0_EDMA0_QM_CQ_CFG0_3 0x41CA0EC

#define mmDCORE0_EDMA0_QM_CQ_CFG0_4 0x41CA0F0

#define mmDCORE0_EDMA0_QM_CQ_STS0_0 0x41CA0F4

#define mmDCORE0_EDMA0_QM_CQ_STS0_1 0x41CA0F8

#define mmDCORE0_EDMA0_QM_CQ_STS0_2 0x41CA0FC

#define mmDCORE0_EDMA0_QM_CQ_STS0_3 0x41CA100

#define mmDCORE0_EDMA0_QM_CQ_STS0_4 0x41CA104

#define mmDCORE0_EDMA0_QM_CQ_CFG1_0 0x41CA108

#define mmDCORE0_EDMA0_QM_CQ_CFG1_1 0x41CA10C

#define mmDCORE0_EDMA0_QM_CQ_CFG1_2 0x41CA110

#define mmDCORE0_EDMA0_QM_CQ_CFG1_3 0x41CA114

#define mmDCORE0_EDMA0_QM_CQ_CFG1_4 0x41CA118

#define mmDCORE0_EDMA0_QM_CQ_STS1_0 0x41CA11C

#define mmDCORE0_EDMA0_QM_CQ_STS1_1 0x41CA120

#define mmDCORE0_EDMA0_QM_CQ_STS1_2 0x41CA124

#define mmDCORE0_EDMA0_QM_CQ_STS1_3 0x41CA128

#define mmDCORE0_EDMA0_QM_CQ_STS1_4 0x41CA12C

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_0 0x41CA150

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_0 0x41CA154

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_0 0x41CA158

#define mmDCORE0_EDMA0_QM_CQ_CTL_0 0x41CA15C

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_1 0x41CA160

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_1 0x41CA164

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_1 0x41CA168

#define mmDCORE0_EDMA0_QM_CQ_CTL_1 0x41CA16C

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_2 0x41CA170

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_2 0x41CA174

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_2 0x41CA178

#define mmDCORE0_EDMA0_QM_CQ_CTL_2 0x41CA17C

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_3 0x41CA180

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_3 0x41CA184

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_3 0x41CA188

#define mmDCORE0_EDMA0_QM_CQ_CTL_3 0x41CA18C

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_4 0x41CA190

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_4 0x41CA194

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_4 0x41CA198

#define mmDCORE0_EDMA0_QM_CQ_CTL_4 0x41CA19C

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_0 0x41CA1A0

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_1 0x41CA1A4

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_2 0x41CA1A8

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_3 0x41CA1AC

#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_4 0x41CA1B0

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_0 0x41CA1B4

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_1 0x41CA1B8

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_2 0x41CA1BC

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_3 0x41CA1C0

#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_4 0x41CA1C4

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_0 0x41CA1C8

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_1 0x41CA1CC

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_2 0x41CA1D0

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_3 0x41CA1D4

#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_4 0x41CA1D8

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_0 0x41CA1DC

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_1 0x41CA1E0

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_2 0x41CA1E4

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_3 0x41CA1E8

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_4 0x41CA1EC

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x41CA1F0

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x41CA1F4

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x41CA1F8

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x41CA1FC

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x41CA200

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x41CA204

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x41CA208

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x41CA20C

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x41CA210

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x41CA214

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x41CA218

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x41CA21C

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x41CA220

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x41CA224

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x41CA228

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x41CA22C

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x41CA230

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x41CA234

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x41CA238

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x41CA23C

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x41CA240

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x41CA244

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x41CA248

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x41CA24C

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x41CA250

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x41CA254

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x41CA258

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x41CA25C

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x41CA260

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x41CA264

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x41CA268

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x41CA26C

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x41CA270

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x41CA274

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x41CA278

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x41CA27C

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x41CA280

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x41CA284

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x41CA288

#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x41CA28C

#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0 0x41CA290

#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1 0x41CA294

#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2 0x41CA298

#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3 0x41CA29C

#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4 0x41CA2A0

#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0 0x41CA2A4

#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1 0x41CA2A8

#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2 0x41CA2AC

#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3 0x41CA2B0

#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4 0x41CA2B4

#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0 0x41CA2B8

#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1 0x41CA2BC

#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2 0x41CA2C0

#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3 0x41CA2C4

#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4 0x41CA2C8

#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0 0x41CA2CC

#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1 0x41CA2D0

#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2 0x41CA2D4

#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3 0x41CA2D8

#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4 0x41CA2DC

#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0 0x41CA2E0

#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1 0x41CA2E4

#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2 0x41CA2E8

#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3 0x41CA2EC

#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4 0x41CA2F0

#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0 0x41CA2F4

#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1 0x41CA2F8

#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2 0x41CA2FC

#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3 0x41CA300

#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4 0x41CA304

#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0 0x41CA308

#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1 0x41CA30C

#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2 0x41CA310

#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3 0x41CA314

#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4 0x41CA318

#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0 0x41CA31C

#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1 0x41CA320

#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2 0x41CA324

#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3 0x41CA328

#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4 0x41CA32C

#define mmDCORE0_EDMA0_QM_CP_BARRIER_CFG 0x41CA330

#define mmDCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x41CA334

#define mmDCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x41CA338

#define mmDCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x41CA33C

#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x41CA340

#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x41CA344

#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x41CA348

#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x41CA34C

#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x41CA350

#define mmDCORE0_EDMA0_QM_CP_STS_0 0x41CA368

#define mmDCORE0_EDMA0_QM_CP_STS_1 0x41CA36C

#define mmDCORE0_EDMA0_QM_CP_STS_2 0x41CA370

#define mmDCORE0_EDMA0_QM_CP_STS_3 0x41CA374

#define mmDCORE0_EDMA0_QM_CP_STS_4 0x41CA378

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_0 0x41CA37C

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_1 0x41CA380

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_2 0x41CA384

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_3 0x41CA388

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_4 0x41CA38C

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_0 0x41CA390

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_1 0x41CA394

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_2 0x41CA398

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_3 0x41CA39C

#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_4 0x41CA3A0

#define mmDCORE0_EDMA0_QM_CP_PRED_0 0x41CA3A4

#define mmDCORE0_EDMA0_QM_CP_PRED_1 0x41CA3A8

#define mmDCORE0_EDMA0_QM_CP_PRED_2 0x41CA3AC

#define mmDCORE0_EDMA0_QM_CP_PRED_3 0x41CA3B0

#define mmDCORE0_EDMA0_QM_CP_PRED_4 0x41CA3B4

#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0 0x41CA3B8

#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1 0x41CA3BC

#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2 0x41CA3C0

#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3 0x41CA3C4

#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4 0x41CA3C8

#define mmDCORE0_EDMA0_QM_CP_DBG_0_0 0x41CA3CC

#define mmDCORE0_EDMA0_QM_CP_DBG_0_1 0x41CA3D0

#define mmDCORE0_EDMA0_QM_CP_DBG_0_2 0x41CA3D4

#define mmDCORE0_EDMA0_QM_CP_DBG_0_3 0x41CA3D8

#define mmDCORE0_EDMA0_QM_CP_DBG_0_4 0x41CA3DC

#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_0 0x41CA3E0

#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_1 0x41CA3E4

#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_2 0x41CA3E8

#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_3 0x41CA3EC

#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_4 0x41CA3F0

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_0 0x41CA3F4

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_1 0x41CA3F8

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_2 0x41CA3FC

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_3 0x41CA400

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_4 0x41CA404

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_0 0x41CA408

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_1 0x41CA40C

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_2 0x41CA410

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_3 0x41CA414

#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_4 0x41CA418

#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_0 0x41CA41C

#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_1 0x41CA420

#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_2 0x41CA424

#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_3 0x41CA428

#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_0 0x41CA42C

#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_1 0x41CA430

#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_2 0x41CA434

#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_3 0x41CA438

#define mmDCORE0_EDMA0_QM_PQC_SIZE_0 0x41CA43C

#define mmDCORE0_EDMA0_QM_PQC_SIZE_1 0x41CA440

#define mmDCORE0_EDMA0_QM_PQC_SIZE_2 0x41CA444

#define mmDCORE0_EDMA0_QM_PQC_SIZE_3 0x41CA448

#define mmDCORE0_EDMA0_QM_PQC_PI_0 0x41CA44C

#define mmDCORE0_EDMA0_QM_PQC_PI_1 0x41CA450

#define mmDCORE0_EDMA0_QM_PQC_PI_2 0x41CA454

#define mmDCORE0_EDMA0_QM_PQC_PI_3 0x41CA458

#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_0 0x41CA45C

#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_1 0x41CA460

#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_2 0x41CA464

#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_3 0x41CA468

#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_0 0x41CA46C

#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_1 0x41CA470

#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_2 0x41CA474

#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_3 0x41CA478

#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_0 0x41CA47C

#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_1 0x41CA480

#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_2 0x41CA484

#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_3 0x41CA488

#define mmDCORE0_EDMA0_QM_PQC_CFG 0x41CA48C

#define mmDCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND 0x41CA490

#define mmDCORE0_EDMA0_QM_ARB_MASK 0x41CA4A0

#define mmDCORE0_EDMA0_QM_ARB_CFG_0 0x41CA4A4

#define mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH 0x41CA4A8

#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0 0x41CA4AC

#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1 0x41CA4B0

#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2 0x41CA4B4

#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3 0x41CA4B8

#define mmDCORE0_EDMA0_QM_ARB_CFG_1 0x41CA4BC

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_0 0x41CA4C0

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_1 0x41CA4C4

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_2 0x41CA4C8

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_3 0x41CA4CC

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_4 0x41CA4D0

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_5 0x41CA4D4

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_6 0x41CA4D8

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_7 0x41CA4DC

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_8 0x41CA4E0

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_9 0x41CA4E4

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_10 0x41CA4E8

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_11 0x41CA4EC

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_12 0x41CA4F0

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_13 0x41CA4F4

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_14 0x41CA4F8

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_15 0x41CA4FC

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_16 0x41CA500

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_17 0x41CA504

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_18 0x41CA508

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_19 0x41CA50C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_20 0x41CA510

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_21 0x41CA514

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_22 0x41CA518

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_23 0x41CA51C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_24 0x41CA520

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_25 0x41CA524

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_26 0x41CA528

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_27 0x41CA52C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_28 0x41CA530

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_29 0x41CA534

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_30 0x41CA538

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_31 0x41CA53C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_32 0x41CA540

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_33 0x41CA544

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_34 0x41CA548

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_35 0x41CA54C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_36 0x41CA550

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_37 0x41CA554

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_38 0x41CA558

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_39 0x41CA55C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_40 0x41CA560

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_41 0x41CA564

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_42 0x41CA568

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_43 0x41CA56C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_44 0x41CA570

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_45 0x41CA574

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_46 0x41CA578

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_47 0x41CA57C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_48 0x41CA580

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_49 0x41CA584

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_50 0x41CA588

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_51 0x41CA58C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_52 0x41CA590

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_53 0x41CA594

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_54 0x41CA598

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_55 0x41CA59C

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_56 0x41CA5A0

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_57 0x41CA5A4

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_58 0x41CA5A8

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_59 0x41CA5AC

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_60 0x41CA5B0

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_61 0x41CA5B4

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_62 0x41CA5B8

#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_63 0x41CA5BC

#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC 0x41CA5E0

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x41CA5E4

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x41CA5E8

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x41CA5EC

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x41CA5F0

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x41CA5F4

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x41CA5F8

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x41CA5FC

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x41CA600

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x41CA604

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x41CA608

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x41CA60C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x41CA610

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x41CA614

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x41CA618

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x41CA61C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x41CA620

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x41CA624

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x41CA628

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x41CA62C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x41CA630

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x41CA634

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x41CA638

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x41CA63C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x41CA640

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x41CA644

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x41CA648

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x41CA64C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x41CA650

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x41CA654

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x41CA658

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x41CA65C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x41CA660

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x41CA664

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x41CA668

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x41CA66C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x41CA670

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x41CA674

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x41CA678

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x41CA67C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x41CA680

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x41CA684

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x41CA688

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x41CA68C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x41CA690

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x41CA694

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x41CA698

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x41CA69C

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x41CA6A0

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x41CA6A4

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x41CA6A8

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x41CA6AC

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x41CA6B0

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x41CA6B4

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x41CA6B8

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x41CA6BC

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x41CA6C0

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x41CA6C4

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x41CA6C8

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x41CA6CC

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x41CA6D0

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x41CA6D4

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x41CA6D8

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x41CA6DC

#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x41CA6E0

#define mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x41CA704

#define mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN 0x41CA708

#define mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 0x41CA70C

#define mmDCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT 0x41CA710

#define mmDCORE0_EDMA0_QM_ARB_SLV_ID 0x41CA714

#define mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER 0x41CA718

#define mmDCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x41CA744

#define mmDCORE0_EDMA0_QM_ARB_BASE_LO 0x41CA754

#define mmDCORE0_EDMA0_QM_ARB_BASE_HI 0x41CA758

#define mmDCORE0_EDMA0_QM_ARB_STATE_STS 0x41CA780

#define mmDCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x41CA784

#define mmDCORE0_EDMA0_QM_ARB_MSG_STS 0x41CA788

#define mmDCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x41CA78C

#define mmDCORE0_EDMA0_QM_ARB_ERR_CAUSE 0x41CA79C

#define mmDCORE0_EDMA0_QM_ARB_ERR_MSG_EN 0x41CA7A0

#define mmDCORE0_EDMA0_QM_ARB_ERR_STS_DRP 0x41CA7A8

#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_STS 0x41CA7B0

#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 0x41CA7B4

#define mmDCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG 0x41CA7FC

#define mmDCORE0_EDMA0_QM_ARC_CQ_CFG0 0x41CA800

#define mmDCORE0_EDMA0_QM_ARC_CQ_CFG1 0x41CA804

#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO 0x41CA808

#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI 0x41CA80C

#define mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE 0x41CA810

#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL 0x41CA814

#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS 0x41CA81C

#define mmDCORE0_EDMA0_QM_ARC_CQ_STS0 0x41CA820

#define mmDCORE0_EDMA0_QM_ARC_CQ_STS1 0x41CA824

#define mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS 0x41CA828

#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS 0x41CA82C

#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS 0x41CA830

#define mmDCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI 0x41CA834

#define mmDCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO 0x41CA838

#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x41CA83C

#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x41CA840

#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x41CA844

#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x41CA848

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x41CA84C

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x41CA850

#define mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI 0x41CA854

#define mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO 0x41CA858

#define mmDCORE0_EDMA0_QM_ADDR_OVRD 0x41CA85C

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0 0x41CA860

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1 0x41CA864

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2 0x41CA868

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3 0x41CA86C

#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4 0x41CA870

#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI 0x41CA874

#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_0 0x41CA878

#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_1 0x41CA87C

#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_2 0x41CA880

#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_3 0x41CA884

#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_4 0x41CA888

#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI 0x41CA88C

#define mmDCORE0_EDMA0_QM_CP_CFG 0x41CA890

#define mmDCORE0_EDMA0_QM_CP_EXT_SWITCH 0x41CA894

#define mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET 0x41CA898

#define mmDCORE0_EDMA0_QM_CP_SWITCH_WD 0x41CA89C

#define mmDCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO 0x41CA8A4

#define mmDCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI 0x41CA8A8

#define mmDCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI 0x41CA8AC

#define mmDCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO 0x41CA8B0

#define mmDCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x41CA8B4

#define mmDCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x41CA8B8

#define mmDCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x41CA8BC

#define mmDCORE0_EDMA0_QM_QM_BASE_ADDR_HI 0x41CA8C0

#define mmDCORE0_EDMA0_QM_QM_BASE_ADDR_LO 0x41CA8C4

#define mmDCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x41CA8C8

#define mmDCORE0_EDMA0_QM_PQC_STS_0_0 0x41CA8D0

#define mmDCORE0_EDMA0_QM_PQC_STS_0_1 0x41CA8D4

#define mmDCORE0_EDMA0_QM_PQC_STS_0_2 0x41CA8D8

#define mmDCORE0_EDMA0_QM_PQC_STS_0_3 0x41CA8DC

#define mmDCORE0_EDMA0_QM_PQC_STS_1_0 0x41CA8E0

#define mmDCORE0_EDMA0_QM_PQC_STS_1_1 0x41CA8E4

#define mmDCORE0_EDMA0_QM_PQC_STS_1_2 0x41CA8E8

#define mmDCORE0_EDMA0_QM_PQC_STS_1_3 0x41CA8EC

#define mmDCORE0_EDMA0_QM_SEI_STATUS 0x41CA8F0

#define mmDCORE0_EDMA0_QM_SEI_MASK 0x41CA8F4

#define mmDCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO 0x41CAD00

#define mmDCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI 0x41CAD04

#define mmDCORE0_EDMA0_QM_GLBL_ERR_WDATA 0x41CAD08

#define mmDCORE0_EDMA0_QM_L2H_MASK_LO 0x41CAD14

#define mmDCORE0_EDMA0_QM_L2H_MASK_HI 0x41CAD18

#define mmDCORE0_EDMA0_QM_L2H_CMPR_LO 0x41CAD1C

#define mmDCORE0_EDMA0_QM_L2H_CMPR_HI 0x41CAD20

#define mmDCORE0_EDMA0_QM_LOCAL_RANGE_BASE 0x41CAD24

#define mmDCORE0_EDMA0_QM_LOCAL_RANGE_SIZE 0x41CAD28

#define mmDCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x41CAD30

#define mmDCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x41CAD34

#define mmDCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x41CAD38

#define mmDCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x41CAD3C

#define mmDCORE0_EDMA0_QM_IND_GW_APB_CFG 0x41CAD40

#define mmDCORE0_EDMA0_QM_IND_GW_APB_WDATA 0x41CAD44

#define mmDCORE0_EDMA0_QM_IND_GW_APB_RDATA 0x41CAD48

#define mmDCORE0_EDMA0_QM_IND_GW_APB_STATUS 0x41CAD4C

#define mmDCORE0_EDMA0_QM_PERF_CNT_FREE_LO 0x41CAD60

#define mmDCORE0_EDMA0_QM_PERF_CNT_FREE_HI 0x41CAD64

#define mmDCORE0_EDMA0_QM_PERF_CNT_IDLE_LO 0x41CAD68

#define mmDCORE0_EDMA0_QM_PERF_CNT_IDLE_HI 0x41CAD6C

#define mmDCORE0_EDMA0_QM_PERF_CNT_CFG 0x41CAD70

#endif /* ASIC_REG_DCORE0_EDMA0_QM_REGS_H_ */