summaryrefslogtreecommitdiff
path: root/drivers/clk/mediatek/clk-mt8183-ipu_adl.c
blob: 8c4fd96df821e1d631f4e92544856b32faf0e9dc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <weiyi.lu@mediatek.com>

#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include "clk-mtk.h"
#include "clk-gate.h"

#include <dt-bindings/clock/mt8183-clk.h>

static const struct mtk_gate_regs ipu_adl_cg_regs = {
	.set_ofs = 0x204,
	.clr_ofs = 0x204,
	.sta_ofs = 0x204,
};

#define GATE_IPU_ADL_I(_id, _name, _parent, _shift)		\
	GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift,	\
		&mtk_clk_gate_ops_no_setclr_inv)

static const struct mtk_gate ipu_adl_clks[] = {
	GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
};

static const struct mtk_clk_desc ipu_adl_desc = {
	.clks = ipu_adl_clks,
	.num_clks = ARRAY_SIZE(ipu_adl_clks),
};

static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
	{
		.compatible = "mediatek,mt8183-ipu_adl",
		.data = &ipu_adl_desc,
	}, {
		/* sentinel */
	}
};

static struct platform_driver clk_mt8183_ipu_adl_drv = {
	.probe = mtk_clk_simple_probe,
	.remove = mtk_clk_simple_remove,
	.driver = {
		.name = "clk-mt8183-ipu_adl",
		.of_match_table = of_match_clk_mt8183_ipu_adl,
	},
};

builtin_platform_driver(clk_mt8183_ipu_adl_drv);