summaryrefslogtreecommitdiff
path: root/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h
blob: 4b553927d2e0edaadb17fa29fc741c687e453bb0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */

/* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200.
 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty)
 */

#ifndef _LAN966X_REGS_H_
#define _LAN966X_REGS_H_

#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>

enum lan966x_target {
	TARGET_AFI = 2,
	TARGET_ANA = 3,
	TARGET_CHIP_TOP = 5,
	TARGET_CPU = 6,
	TARGET_DEV = 13,
	TARGET_FDMA = 21,
	TARGET_GCB = 27,
	TARGET_ORG = 36,
	TARGET_PTP = 41,
	TARGET_QS = 42,
	TARGET_QSYS = 46,
	TARGET_REW = 47,
	TARGET_SYS = 52,
	TARGET_VCAP = 61,
	NUM_TARGETS = 66
};

#define __REG(...)    __VA_ARGS__

/*      AFI:PORT_TBL:PORT_FRM_OUT */
#define AFI_PORT_FRM_OUT(g)       __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4)

#define AFI_PORT_FRM_OUT_FRM_OUT_CNT             GENMASK(26, 16)
#define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\
	FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
#define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\
	FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)

/*      AFI:PORT_TBL:PORT_CFG */
#define AFI_PORT_CFG(g)           __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4)

#define AFI_PORT_CFG_FC_SKIP_TTI_INJ             BIT(16)
#define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\
	FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
#define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\
	FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)

#define AFI_PORT_CFG_FRM_OUT_MAX                 GENMASK(9, 0)
#define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\
	FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
#define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\
	FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x)

/*      ANA:ANA:ADVLEARN */
#define ANA_ADVLEARN              __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4)

#define ANA_ADVLEARN_VLAN_CHK                    BIT(0)
#define ANA_ADVLEARN_VLAN_CHK_SET(x)\
	FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x)
#define ANA_ADVLEARN_VLAN_CHK_GET(x)\
	FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x)

/*      ANA:ANA:VLANMASK */
#define ANA_VLANMASK              __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4)

/*      ANA:ANA:ANAINTR */
#define ANA_ANAINTR               __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4)

#define ANA_ANAINTR_INTR                         BIT(1)
#define ANA_ANAINTR_INTR_SET(x)\
	FIELD_PREP(ANA_ANAINTR_INTR, x)
#define ANA_ANAINTR_INTR_GET(x)\
	FIELD_GET(ANA_ANAINTR_INTR, x)

#define ANA_ANAINTR_INTR_ENA                     BIT(0)
#define ANA_ANAINTR_INTR_ENA_SET(x)\
	FIELD_PREP(ANA_ANAINTR_INTR_ENA, x)
#define ANA_ANAINTR_INTR_ENA_GET(x)\
	FIELD_GET(ANA_ANAINTR_INTR_ENA, x)

/*      ANA:ANA:AUTOAGE */
#define ANA_AUTOAGE               __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4)

#define ANA_AUTOAGE_AGE_PERIOD                   GENMASK(20, 1)
#define ANA_AUTOAGE_AGE_PERIOD_SET(x)\
	FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x)
#define ANA_AUTOAGE_AGE_PERIOD_GET(x)\
	FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x)

/*      ANA:ANA:MIRRORPORTS */
#define ANA_MIRRORPORTS           __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 60, 0, 1, 4)

#define ANA_MIRRORPORTS_MIRRORPORTS              GENMASK(8, 0)
#define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\
	FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x)
#define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\
	FIELD_GET(ANA_MIRRORPORTS_MIRRORPORTS, x)

/*      ANA:ANA:EMIRRORPORTS */
#define ANA_EMIRRORPORTS          __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 64, 0, 1, 4)

#define ANA_EMIRRORPORTS_EMIRRORPORTS            GENMASK(8, 0)
#define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\
	FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x)
#define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\
	FIELD_GET(ANA_EMIRRORPORTS_EMIRRORPORTS, x)

/*      ANA:ANA:FLOODING */
#define ANA_FLOODING(r)           __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4)

#define ANA_FLOODING_FLD_UNICAST                 GENMASK(17, 12)
#define ANA_FLOODING_FLD_UNICAST_SET(x)\
	FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x)
#define ANA_FLOODING_FLD_UNICAST_GET(x)\
	FIELD_GET(ANA_FLOODING_FLD_UNICAST, x)

#define ANA_FLOODING_FLD_BROADCAST               GENMASK(11, 6)
#define ANA_FLOODING_FLD_BROADCAST_SET(x)\
	FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x)
#define ANA_FLOODING_FLD_BROADCAST_GET(x)\
	FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x)

#define ANA_FLOODING_FLD_MULTICAST               GENMASK(5, 0)
#define ANA_FLOODING_FLD_MULTICAST_SET(x)\
	FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x)
#define ANA_FLOODING_FLD_MULTICAST_GET(x)\
	FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x)

/*      ANA:ANA:FLOODING_IPMC */
#define ANA_FLOODING_IPMC         __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4)

#define ANA_FLOODING_IPMC_FLD_MC4_CTRL           GENMASK(23, 18)
#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\
	FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\
	FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)

#define ANA_FLOODING_IPMC_FLD_MC4_DATA           GENMASK(17, 12)
#define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\
	FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
#define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\
	FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)

#define ANA_FLOODING_IPMC_FLD_MC6_CTRL           GENMASK(11, 6)
#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\
	FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\
	FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)

#define ANA_FLOODING_IPMC_FLD_MC6_DATA           GENMASK(5, 0)
#define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\
	FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
#define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\
	FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)

/*      ANA:PGID:PGID */
#define ANA_PGID(g)               __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4)

#define ANA_PGID_PGID                            GENMASK(8, 0)
#define ANA_PGID_PGID_SET(x)\
	FIELD_PREP(ANA_PGID_PGID, x)
#define ANA_PGID_PGID_GET(x)\
	FIELD_GET(ANA_PGID_PGID, x)

/*      ANA:PGID:PGID_CFG */
#define ANA_PGID_CFG(g)           __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4)

#define ANA_PGID_CFG_OBEY_VLAN                   BIT(0)
#define ANA_PGID_CFG_OBEY_VLAN_SET(x)\
	FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x)
#define ANA_PGID_CFG_OBEY_VLAN_GET(x)\
	FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x)

/*      ANA:ANA_TABLES:MACHDATA */
#define ANA_MACHDATA              __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4)

/*      ANA:ANA_TABLES:MACLDATA */
#define ANA_MACLDATA              __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4)

/*      ANA:ANA_TABLES:MACACCESS */
#define ANA_MACACCESS             __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4)

#define ANA_MACACCESS_CHANGE2SW                  BIT(17)
#define ANA_MACACCESS_CHANGE2SW_SET(x)\
	FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x)
#define ANA_MACACCESS_CHANGE2SW_GET(x)\
	FIELD_GET(ANA_MACACCESS_CHANGE2SW, x)

#define ANA_MACACCESS_MAC_CPU_COPY               BIT(16)
#define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\
	FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x)
#define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\
	FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x)

#define ANA_MACACCESS_VALID                      BIT(12)
#define ANA_MACACCESS_VALID_SET(x)\
	FIELD_PREP(ANA_MACACCESS_VALID, x)
#define ANA_MACACCESS_VALID_GET(x)\
	FIELD_GET(ANA_MACACCESS_VALID, x)

#define ANA_MACACCESS_ENTRYTYPE                  GENMASK(11, 10)
#define ANA_MACACCESS_ENTRYTYPE_SET(x)\
	FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x)
#define ANA_MACACCESS_ENTRYTYPE_GET(x)\
	FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x)

#define ANA_MACACCESS_DEST_IDX                   GENMASK(9, 4)
#define ANA_MACACCESS_DEST_IDX_SET(x)\
	FIELD_PREP(ANA_MACACCESS_DEST_IDX, x)
#define ANA_MACACCESS_DEST_IDX_GET(x)\
	FIELD_GET(ANA_MACACCESS_DEST_IDX, x)

#define ANA_MACACCESS_MAC_TABLE_CMD              GENMASK(3, 0)
#define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\
	FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x)
#define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\
	FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x)

/*      ANA:ANA_TABLES:MACTINDX */
#define ANA_MACTINDX              __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4)

#define ANA_MACTINDX_BUCKET                      GENMASK(12, 11)
#define ANA_MACTINDX_BUCKET_SET(x)\
	FIELD_PREP(ANA_MACTINDX_BUCKET, x)
#define ANA_MACTINDX_BUCKET_GET(x)\
	FIELD_GET(ANA_MACTINDX_BUCKET, x)

#define ANA_MACTINDX_M_INDEX                     GENMASK(10, 0)
#define ANA_MACTINDX_M_INDEX_SET(x)\
	FIELD_PREP(ANA_MACTINDX_M_INDEX, x)
#define ANA_MACTINDX_M_INDEX_GET(x)\
	FIELD_GET(ANA_MACTINDX_M_INDEX, x)

/*      ANA:ANA_TABLES:VLAN_PORT_MASK */
#define ANA_VLAN_PORT_MASK        __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4)

#define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK        GENMASK(8, 0)
#define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\
	FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x)
#define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\
	FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x)

/*      ANA:ANA_TABLES:VLANACCESS */
#define ANA_VLANACCESS            __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4)

#define ANA_VLANACCESS_VLAN_TBL_CMD              GENMASK(1, 0)
#define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\
	FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x)
#define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\
	FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x)

/*      ANA:ANA_TABLES:VLANTIDX */
#define ANA_VLANTIDX              __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4)

#define ANA_VLANTIDX_VLAN_PGID_CPU_DIS           BIT(18)
#define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\
	FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x)
#define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\
	FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x)

#define ANA_VLANTIDX_V_INDEX                     GENMASK(11, 0)
#define ANA_VLANTIDX_V_INDEX_SET(x)\
	FIELD_PREP(ANA_VLANTIDX_V_INDEX, x)
#define ANA_VLANTIDX_V_INDEX_GET(x)\
	FIELD_GET(ANA_VLANTIDX_V_INDEX, x)

/*      ANA:PORT:VLAN_CFG */
#define ANA_VLAN_CFG(g)           __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4)

#define ANA_VLAN_CFG_VLAN_AWARE_ENA              BIT(20)
#define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\
	FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x)
#define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\
	FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x)

#define ANA_VLAN_CFG_VLAN_POP_CNT                GENMASK(19, 18)
#define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\
	FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x)
#define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\
	FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x)

#define ANA_VLAN_CFG_VLAN_PCP                    GENMASK(15, 13)
#define ANA_VLAN_CFG_VLAN_PCP_SET(x)\
	FIELD_PREP(ANA_VLAN_CFG_VLAN_PCP, x)
#define ANA_VLAN_CFG_VLAN_PCP_GET(x)\
	FIELD_GET(ANA_VLAN_CFG_VLAN_PCP, x)

#define ANA_VLAN_CFG_VLAN_DEI                    BIT(12)
#define ANA_VLAN_CFG_VLAN_DEI_SET(x)\
	FIELD_PREP(ANA_VLAN_CFG_VLAN_DEI, x)
#define ANA_VLAN_CFG_VLAN_DEI_GET(x)\
	FIELD_GET(ANA_VLAN_CFG_VLAN_DEI, x)

#define ANA_VLAN_CFG_VLAN_VID                    GENMASK(11, 0)
#define ANA_VLAN_CFG_VLAN_VID_SET(x)\
	FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x)
#define ANA_VLAN_CFG_VLAN_VID_GET(x)\
	FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x)

/*      ANA:PORT:DROP_CFG */
#define ANA_DROP_CFG(g)           __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4)

#define ANA_DROP_CFG_DROP_UNTAGGED_ENA           BIT(6)
#define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\
	FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x)
#define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\
	FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x)

#define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA      BIT(3)
#define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\
	FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x)
#define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\
	FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x)

#define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA      BIT(2)
#define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\
	FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x)
#define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\
	FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x)

#define ANA_DROP_CFG_DROP_MC_SMAC_ENA            BIT(0)
#define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\
	FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
#define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\
	FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)

/*      ANA:PORT:QOS_CFG */
#define ANA_QOS_CFG(g)            __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 8, 0, 1, 4)

#define ANA_QOS_CFG_DP_DEFAULT_VAL               BIT(8)
#define ANA_QOS_CFG_DP_DEFAULT_VAL_SET(x)\
	FIELD_PREP(ANA_QOS_CFG_DP_DEFAULT_VAL, x)
#define ANA_QOS_CFG_DP_DEFAULT_VAL_GET(x)\
	FIELD_GET(ANA_QOS_CFG_DP_DEFAULT_VAL, x)

#define ANA_QOS_CFG_QOS_DEFAULT_VAL              GENMASK(7, 5)
#define ANA_QOS_CFG_QOS_DEFAULT_VAL_SET(x)\
	FIELD_PREP(ANA_QOS_CFG_QOS_DEFAULT_VAL, x)
#define ANA_QOS_CFG_QOS_DEFAULT_VAL_GET(x)\
	FIELD_GET(ANA_QOS_CFG_QOS_DEFAULT_VAL, x)

#define ANA_QOS_CFG_QOS_DSCP_ENA                 BIT(4)
#define ANA_QOS_CFG_QOS_DSCP_ENA_SET(x)\
	FIELD_PREP(ANA_QOS_CFG_QOS_DSCP_ENA, x)
#define ANA_QOS_CFG_QOS_DSCP_ENA_GET(x)\
	FIELD_GET(ANA_QOS_CFG_QOS_DSCP_ENA, x)

#define ANA_QOS_CFG_QOS_PCP_ENA                  BIT(3)
#define ANA_QOS_CFG_QOS_PCP_ENA_SET(x)\
	FIELD_PREP(ANA_QOS_CFG_QOS_PCP_ENA, x)
#define ANA_QOS_CFG_QOS_PCP_ENA_GET(x)\
	FIELD_GET(ANA_QOS_CFG_QOS_PCP_ENA, x)

#define ANA_QOS_CFG_DSCP_REWR_CFG                GENMASK(1, 0)
#define ANA_QOS_CFG_DSCP_REWR_CFG_SET(x)\
	FIELD_PREP(ANA_QOS_CFG_DSCP_REWR_CFG, x)
#define ANA_QOS_CFG_DSCP_REWR_CFG_GET(x)\
	FIELD_GET(ANA_QOS_CFG_DSCP_REWR_CFG, x)

/*      ANA:PORT:VCAP_CFG */
#define ANA_VCAP_CFG(g)           __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 12, 0, 1, 4)

#define ANA_VCAP_CFG_S1_ENA                      BIT(14)
#define ANA_VCAP_CFG_S1_ENA_SET(x)\
	FIELD_PREP(ANA_VCAP_CFG_S1_ENA, x)
#define ANA_VCAP_CFG_S1_ENA_GET(x)\
	FIELD_GET(ANA_VCAP_CFG_S1_ENA, x)

/*      ANA:PORT:VCAP_S1_KEY_CFG */
#define ANA_VCAP_S1_CFG(g, r)     __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 16, r, 3, 4)

#define ANA_VCAP_S1_CFG_KEY_RT_CFG               GENMASK(11, 9)
#define ANA_VCAP_S1_CFG_KEY_RT_CFG_SET(x)\
	FIELD_PREP(ANA_VCAP_S1_CFG_KEY_RT_CFG, x)
#define ANA_VCAP_S1_CFG_KEY_RT_CFG_GET(x)\
	FIELD_GET(ANA_VCAP_S1_CFG_KEY_RT_CFG, x)

#define ANA_VCAP_S1_CFG_KEY_IP6_CFG              GENMASK(8, 6)
#define ANA_VCAP_S1_CFG_KEY_IP6_CFG_SET(x)\
	FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x)
#define ANA_VCAP_S1_CFG_KEY_IP6_CFG_GET(x)\
	FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x)

#define ANA_VCAP_S1_CFG_KEY_IP4_CFG              GENMASK(5, 3)
#define ANA_VCAP_S1_CFG_KEY_IP4_CFG_SET(x)\
	FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x)
#define ANA_VCAP_S1_CFG_KEY_IP4_CFG_GET(x)\
	FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x)

#define ANA_VCAP_S1_CFG_KEY_OTHER_CFG            GENMASK(2, 0)
#define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_SET(x)\
	FIELD_PREP(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x)
#define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_GET(x)\
	FIELD_GET(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x)

/*      ANA:PORT:VCAP_S2_CFG */
#define ANA_VCAP_S2_CFG(g)        __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 28, 0, 1, 4)

#define ANA_VCAP_S2_CFG_ISDX_ENA                 GENMASK(20, 19)
#define ANA_VCAP_S2_CFG_ISDX_ENA_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_ISDX_ENA, x)
#define ANA_VCAP_S2_CFG_ISDX_ENA_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_ISDX_ENA, x)

#define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA          GENMASK(18, 17)
#define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x)
#define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x)

#define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA        GENMASK(16, 15)
#define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x)
#define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x)

#define ANA_VCAP_S2_CFG_ENA                      BIT(14)
#define ANA_VCAP_S2_CFG_ENA_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_ENA, x)
#define ANA_VCAP_S2_CFG_ENA_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_ENA, x)

#define ANA_VCAP_S2_CFG_SNAP_DIS                 GENMASK(13, 12)
#define ANA_VCAP_S2_CFG_SNAP_DIS_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_SNAP_DIS, x)
#define ANA_VCAP_S2_CFG_SNAP_DIS_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_SNAP_DIS, x)

#define ANA_VCAP_S2_CFG_ARP_DIS                  GENMASK(11, 10)
#define ANA_VCAP_S2_CFG_ARP_DIS_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_ARP_DIS, x)
#define ANA_VCAP_S2_CFG_ARP_DIS_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_ARP_DIS, x)

#define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS            GENMASK(9, 8)
#define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x)
#define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x)

#define ANA_VCAP_S2_CFG_IP_OTHER_DIS             GENMASK(7, 6)
#define ANA_VCAP_S2_CFG_IP_OTHER_DIS_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x)
#define ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x)

#define ANA_VCAP_S2_CFG_IP6_CFG                  GENMASK(5, 2)
#define ANA_VCAP_S2_CFG_IP6_CFG_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_IP6_CFG, x)
#define ANA_VCAP_S2_CFG_IP6_CFG_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_IP6_CFG, x)

#define ANA_VCAP_S2_CFG_OAM_DIS                  GENMASK(1, 0)
#define ANA_VCAP_S2_CFG_OAM_DIS_SET(x)\
	FIELD_PREP(ANA_VCAP_S2_CFG_OAM_DIS, x)
#define ANA_VCAP_S2_CFG_OAM_DIS_GET(x)\
	FIELD_GET(ANA_VCAP_S2_CFG_OAM_DIS, x)

/*      ANA:PORT:QOS_PCP_DEI_MAP_CFG */
#define ANA_PCP_DEI_CFG(g, r)     __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 32, r, 16, 4)

#define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL           BIT(3)
#define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_SET(x)\
	FIELD_PREP(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x)
#define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_GET(x)\
	FIELD_GET(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x)

#define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL          GENMASK(2, 0)
#define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_SET(x)\
	FIELD_PREP(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x)
#define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_GET(x)\
	FIELD_GET(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x)

/*      ANA:PORT:CPU_FWD_CFG */
#define ANA_CPU_FWD_CFG(g)        __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4)

#define ANA_CPU_FWD_CFG_MLD_REDIR_ENA            BIT(6)
#define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\
	FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x)
#define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\
	FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x)

#define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA           BIT(5)
#define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\
	FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x)
#define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\
	FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x)

#define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA       BIT(4)
#define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\
	FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x)
#define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\
	FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x)

#define ANA_CPU_FWD_CFG_SRC_COPY_ENA             BIT(3)
#define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\
	FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
#define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\
	FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)

/*      ANA:PORT:CPU_FWD_BPDU_CFG */
#define ANA_CPU_FWD_BPDU_CFG(g)   __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4)

/*      ANA:PORT:PORT_CFG */
#define ANA_PORT_CFG(g)           __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4)

#define ANA_PORT_CFG_SRC_MIRROR_ENA              BIT(13)
#define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\
	FIELD_PREP(ANA_PORT_CFG_SRC_MIRROR_ENA, x)
#define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\
	FIELD_GET(ANA_PORT_CFG_SRC_MIRROR_ENA, x)

#define ANA_PORT_CFG_LEARNAUTO                   BIT(6)
#define ANA_PORT_CFG_LEARNAUTO_SET(x)\
	FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x)
#define ANA_PORT_CFG_LEARNAUTO_GET(x)\
	FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x)

#define ANA_PORT_CFG_LEARN_ENA                   BIT(5)
#define ANA_PORT_CFG_LEARN_ENA_SET(x)\
	FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x)
#define ANA_PORT_CFG_LEARN_ENA_GET(x)\
	FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x)

#define ANA_PORT_CFG_RECV_ENA                    BIT(4)
#define ANA_PORT_CFG_RECV_ENA_SET(x)\
	FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x)
#define ANA_PORT_CFG_RECV_ENA_GET(x)\
	FIELD_GET(ANA_PORT_CFG_RECV_ENA, x)

#define ANA_PORT_CFG_PORTID_VAL                  GENMASK(3, 0)
#define ANA_PORT_CFG_PORTID_VAL_SET(x)\
	FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x)
#define ANA_PORT_CFG_PORTID_VAL_GET(x)\
	FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x)

/*      ANA:COMMON:DSCP_REWR_CFG */
#define ANA_DSCP_REWR_CFG(r)      __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 332, r, 16, 4)

#define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL      GENMASK(5, 0)
#define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_SET(x)\
	FIELD_PREP(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x)
#define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_GET(x)\
	FIELD_GET(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x)

/*      ANA:PORT:POL_CFG */
#define ANA_POL_CFG(g)            __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 116, 0, 1, 4)

#define ANA_POL_CFG_PORT_POL_ENA                 BIT(17)
#define ANA_POL_CFG_PORT_POL_ENA_SET(x)\
	FIELD_PREP(ANA_POL_CFG_PORT_POL_ENA, x)
#define ANA_POL_CFG_PORT_POL_ENA_GET(x)\
	FIELD_GET(ANA_POL_CFG_PORT_POL_ENA, x)

#define ANA_POL_CFG_POL_ORDER                    GENMASK(8, 0)
#define ANA_POL_CFG_POL_ORDER_SET(x)\
	FIELD_PREP(ANA_POL_CFG_POL_ORDER, x)
#define ANA_POL_CFG_POL_ORDER_GET(x)\
	FIELD_GET(ANA_POL_CFG_POL_ORDER, x)

/*      ANA:PFC:PFC_CFG */
#define ANA_PFC_CFG(g)            __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4)

#define ANA_PFC_CFG_FC_LINK_SPEED                GENMASK(1, 0)
#define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\
	FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x)
#define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\
	FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x)

/*      ANA:COMMON:AGGR_CFG */
#define ANA_AGGR_CFG              __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 0, 0, 1, 4)

#define ANA_AGGR_CFG_AC_RND_ENA                  BIT(6)
#define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\
	FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x)
#define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\
	FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x)

#define ANA_AGGR_CFG_AC_DMAC_ENA                 BIT(5)
#define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\
	FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x)
#define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\
	FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x)

#define ANA_AGGR_CFG_AC_SMAC_ENA                 BIT(4)
#define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\
	FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x)
#define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\
	FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x)

#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA         BIT(3)
#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\
	FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x)
#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\
	FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x)

#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA           BIT(2)
#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\
	FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x)
#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\
	FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x)

#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA           BIT(1)
#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\
	FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x)
#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\
	FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x)

#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA           BIT(0)
#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\
	FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)
#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\
	FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)

/*      ANA:COMMON:DSCP_CFG */
#define ANA_DSCP_CFG(r)           __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 76, r, 64, 4)

#define ANA_DSCP_CFG_DP_DSCP_VAL                 BIT(11)
#define ANA_DSCP_CFG_DP_DSCP_VAL_SET(x)\
	FIELD_PREP(ANA_DSCP_CFG_DP_DSCP_VAL, x)
#define ANA_DSCP_CFG_DP_DSCP_VAL_GET(x)\
	FIELD_GET(ANA_DSCP_CFG_DP_DSCP_VAL, x)

#define ANA_DSCP_CFG_QOS_DSCP_VAL                GENMASK(10, 8)
#define ANA_DSCP_CFG_QOS_DSCP_VAL_SET(x)\
	FIELD_PREP(ANA_DSCP_CFG_QOS_DSCP_VAL, x)
#define ANA_DSCP_CFG_QOS_DSCP_VAL_GET(x)\
	FIELD_GET(ANA_DSCP_CFG_QOS_DSCP_VAL, x)

#define ANA_DSCP_CFG_DSCP_TRUST_ENA              BIT(1)
#define ANA_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\
	FIELD_PREP(ANA_DSCP_CFG_DSCP_TRUST_ENA, x)
#define ANA_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\
	FIELD_GET(ANA_DSCP_CFG_DSCP_TRUST_ENA, x)

#define ANA_DSCP_CFG_DSCP_REWR_ENA               BIT(0)
#define ANA_DSCP_CFG_DSCP_REWR_ENA_SET(x)\
	FIELD_PREP(ANA_DSCP_CFG_DSCP_REWR_ENA, x)
#define ANA_DSCP_CFG_DSCP_REWR_ENA_GET(x)\
	FIELD_GET(ANA_DSCP_CFG_DSCP_REWR_ENA, x)

/*      ANA:POL:POL_PIR_CFG */
#define ANA_POL_PIR_CFG(g)        __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 0, 0, 1, 4)

#define ANA_POL_PIR_CFG_PIR_RATE                 GENMASK(20, 6)
#define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\
	FIELD_PREP(ANA_POL_PIR_CFG_PIR_RATE, x)
#define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\
	FIELD_GET(ANA_POL_PIR_CFG_PIR_RATE, x)

#define ANA_POL_PIR_CFG_PIR_BURST                GENMASK(5, 0)
#define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\
	FIELD_PREP(ANA_POL_PIR_CFG_PIR_BURST, x)
#define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\
	FIELD_GET(ANA_POL_PIR_CFG_PIR_BURST, x)

/*      ANA:POL:POL_MODE_CFG */
#define ANA_POL_MODE(g)           __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 8, 0, 1, 4)

#define ANA_POL_MODE_DROP_ON_YELLOW_ENA          BIT(11)
#define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\
	FIELD_PREP(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x)
#define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\
	FIELD_GET(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x)

#define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA       BIT(10)
#define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\
	FIELD_PREP(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x)
#define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\
	FIELD_GET(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x)

#define ANA_POL_MODE_IPG_SIZE                    GENMASK(9, 5)
#define ANA_POL_MODE_IPG_SIZE_SET(x)\
	FIELD_PREP(ANA_POL_MODE_IPG_SIZE, x)
#define ANA_POL_MODE_IPG_SIZE_GET(x)\
	FIELD_GET(ANA_POL_MODE_IPG_SIZE, x)

#define ANA_POL_MODE_FRM_MODE                    GENMASK(4, 3)
#define ANA_POL_MODE_FRM_MODE_SET(x)\
	FIELD_PREP(ANA_POL_MODE_FRM_MODE, x)
#define ANA_POL_MODE_FRM_MODE_GET(x)\
	FIELD_GET(ANA_POL_MODE_FRM_MODE, x)

#define ANA_POL_MODE_OVERSHOOT_ENA               BIT(0)
#define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\
	FIELD_PREP(ANA_POL_MODE_OVERSHOOT_ENA, x)
#define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\
	FIELD_GET(ANA_POL_MODE_OVERSHOOT_ENA, x)

/*      ANA:POL:POL_PIR_STATE */
#define ANA_POL_PIR_STATE(g)      __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 12, 0, 1, 4)

#define ANA_POL_PIR_STATE_PIR_LVL                GENMASK(21, 0)
#define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\
	FIELD_PREP(ANA_POL_PIR_STATE_PIR_LVL, x)
#define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\
	FIELD_GET(ANA_POL_PIR_STATE_PIR_LVL, x)

/*      CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */
#define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4)

#define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA      BIT(0)
#define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\
	FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
#define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\
	FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)

/*      DEV:PORT_MODE:CLOCK_CFG */
#define DEV_CLOCK_CFG(t)          __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4)

#define DEV_CLOCK_CFG_MAC_TX_RST                 BIT(7)
#define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\
	FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x)
#define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\
	FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x)

#define DEV_CLOCK_CFG_MAC_RX_RST                 BIT(6)
#define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\
	FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x)
#define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\
	FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x)

#define DEV_CLOCK_CFG_PCS_TX_RST                 BIT(5)
#define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\
	FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x)
#define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\
	FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x)

#define DEV_CLOCK_CFG_PCS_RX_RST                 BIT(4)
#define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\
	FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x)
#define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\
	FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x)

#define DEV_CLOCK_CFG_PORT_RST                   BIT(3)
#define DEV_CLOCK_CFG_PORT_RST_SET(x)\
	FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x)
#define DEV_CLOCK_CFG_PORT_RST_GET(x)\
	FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x)

#define DEV_CLOCK_CFG_LINK_SPEED                 GENMASK(1, 0)
#define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\
	FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x)
#define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\
	FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x)

/*      DEV:MAC_CFG_STATUS:MAC_ENA_CFG */
#define DEV_MAC_ENA_CFG(t)        __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4)

#define DEV_MAC_ENA_CFG_RX_ENA                   BIT(4)
#define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\
	FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x)
#define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\
	FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x)

#define DEV_MAC_ENA_CFG_TX_ENA                   BIT(0)
#define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\
	FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x)
#define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\
	FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x)

/*      DEV:MAC_CFG_STATUS:MAC_MODE_CFG */
#define DEV_MAC_MODE_CFG(t)       __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4)

#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA           BIT(4)
#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
	FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
	FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)

/*      DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
#define DEV_MAC_MAXLEN_CFG(t)     __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4)

#define DEV_MAC_MAXLEN_CFG_MAX_LEN               GENMASK(15, 0)
#define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
	FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
#define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
	FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)

/*      DEV:MAC_CFG_STATUS:MAC_TAGS_CFG */
#define DEV_MAC_TAGS_CFG(t)       __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 12, 0, 1, 4)

#define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA        BIT(1)
#define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\
	FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x)
#define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\
	FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x)

#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA            BIT(0)
#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
	FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
	FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x)

/*      DEV:MAC_CFG_STATUS:MAC_IFG_CFG */
#define DEV_MAC_IFG_CFG(t)        __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4)

#define DEV_MAC_IFG_CFG_TX_IFG                   GENMASK(12, 8)
#define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\
	FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x)
#define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\
	FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x)

#define DEV_MAC_IFG_CFG_RX_IFG2                  GENMASK(7, 4)
#define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\
	FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x)
#define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\
	FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x)

#define DEV_MAC_IFG_CFG_RX_IFG1                  GENMASK(3, 0)
#define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\
	FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x)
#define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\
	FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x)

/*      DEV:MAC_CFG_STATUS:MAC_HDX_CFG */
#define DEV_MAC_HDX_CFG(t)        __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4)

#define DEV_MAC_HDX_CFG_SEED                     GENMASK(23, 16)
#define DEV_MAC_HDX_CFG_SEED_SET(x)\
	FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x)
#define DEV_MAC_HDX_CFG_SEED_GET(x)\
	FIELD_GET(DEV_MAC_HDX_CFG_SEED, x)

#define DEV_MAC_HDX_CFG_SEED_LOAD                BIT(12)
#define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\
	FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x)
#define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\
	FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x)

/*      DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */
#define DEV_FC_MAC_LOW_CFG(t)     __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4)

/*      DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */
#define DEV_FC_MAC_HIGH_CFG(t)    __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4)

/*      DEV:PCS1G_CFG_STATUS:PCS1G_CFG */
#define DEV_PCS1G_CFG(t)          __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4)

#define DEV_PCS1G_CFG_PCS_ENA                    BIT(0)
#define DEV_PCS1G_CFG_PCS_ENA_SET(x)\
	FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x)
#define DEV_PCS1G_CFG_PCS_ENA_GET(x)\
	FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x)

/*      DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */
#define DEV_PCS1G_MODE_CFG(t)     __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4)

#define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA        BIT(0)
#define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
	FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
#define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
	FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)

#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA        BIT(1)
#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\
	FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\
	FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)

/*      DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */
#define DEV_PCS1G_SD_CFG(t)       __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4)

#define DEV_PCS1G_SD_CFG_SD_ENA                  BIT(0)
#define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\
	FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x)
#define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\
	FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x)

/*      DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */
#define DEV_PCS1G_ANEG_CFG(t)     __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4)

#define DEV_PCS1G_ANEG_CFG_ADV_ABILITY           GENMASK(31, 16)
#define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
	FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
#define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
	FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)

#define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA        BIT(8)
#define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
	FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
#define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
	FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)

#define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT      BIT(1)
#define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\
	FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
#define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\
	FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)

#define DEV_PCS1G_ANEG_CFG_ENA                   BIT(0)
#define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\
	FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x)
#define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\
	FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x)

/*      DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */
#define DEV_PCS1G_ANEG_STATUS(t)  __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4)

#define DEV_PCS1G_ANEG_STATUS_LP_ADV             GENMASK(31, 16)
#define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\
	FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
#define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\
	FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)

#define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE      BIT(0)
#define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
	FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
#define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
	FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)

/*      DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */
#define DEV_PCS1G_LINK_STATUS(t)  __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4)

#define DEV_PCS1G_LINK_STATUS_LINK_STATUS        BIT(4)
#define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
	FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
#define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
	FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)

#define DEV_PCS1G_LINK_STATUS_SYNC_STATUS        BIT(0)
#define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
	FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
#define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
	FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)

/*      DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */
#define DEV_PCS1G_STICKY(t)       __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4)

#define DEV_PCS1G_STICKY_LINK_DOWN_STICKY        BIT(4)
#define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
	FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
#define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
	FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)

/*      FDMA:FDMA:FDMA_CH_ACTIVATE */
#define FDMA_CH_ACTIVATE          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)

#define FDMA_CH_ACTIVATE_CH_ACTIVATE             GENMASK(7, 0)
#define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\
	FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
#define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\
	FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)

/*      FDMA:FDMA:FDMA_CH_RELOAD */
#define FDMA_CH_RELOAD            __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)

#define FDMA_CH_RELOAD_CH_RELOAD                 GENMASK(7, 0)
#define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\
	FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
#define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\
	FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)

/*      FDMA:FDMA:FDMA_CH_DISABLE */
#define FDMA_CH_DISABLE           __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)

#define FDMA_CH_DISABLE_CH_DISABLE               GENMASK(7, 0)
#define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\
	FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
#define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\
	FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)

/*      FDMA:FDMA:FDMA_CH_DB_DISCARD */
#define FDMA_CH_DB_DISCARD        __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4)

#define FDMA_CH_DB_DISCARD_DB_DISCARD            GENMASK(7, 0)
#define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\
	FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x)
#define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\
	FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x)

/*      FDMA:FDMA:FDMA_DCB_LLP */
#define FDMA_DCB_LLP(r)           __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4)

/*      FDMA:FDMA:FDMA_DCB_LLP1 */
#define FDMA_DCB_LLP1(r)          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4)

/*      FDMA:FDMA:FDMA_CH_ACTIVE */
#define FDMA_CH_ACTIVE            __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4)

/*      FDMA:FDMA:FDMA_CH_CFG */
#define FDMA_CH_CFG(r)            __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4)

#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY          BIT(4)
#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\
	FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\
	FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)

#define FDMA_CH_CFG_CH_INJ_PORT                  BIT(3)
#define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\
	FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
#define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\
	FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)

#define FDMA_CH_CFG_CH_DCB_DB_CNT                GENMASK(2, 1)
#define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\
	FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
#define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\
	FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)

#define FDMA_CH_CFG_CH_MEM                       BIT(0)
#define FDMA_CH_CFG_CH_MEM_SET(x)\
	FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
#define FDMA_CH_CFG_CH_MEM_GET(x)\
	FIELD_GET(FDMA_CH_CFG_CH_MEM, x)

/*      FDMA:FDMA:FDMA_PORT_CTRL */
#define FDMA_PORT_CTRL(r)         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4)

#define FDMA_PORT_CTRL_INJ_STOP                  BIT(4)
#define FDMA_PORT_CTRL_INJ_STOP_SET(x)\
	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
#define FDMA_PORT_CTRL_INJ_STOP_GET(x)\
	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)

#define FDMA_PORT_CTRL_XTR_STOP                  BIT(2)
#define FDMA_PORT_CTRL_XTR_STOP_SET(x)\
	FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
#define FDMA_PORT_CTRL_XTR_STOP_GET(x)\
	FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)

/*      FDMA:FDMA:FDMA_INTR_DB */
#define FDMA_INTR_DB              __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)

/*      FDMA:FDMA:FDMA_INTR_DB_ENA */
#define FDMA_INTR_DB_ENA          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)

#define FDMA_INTR_DB_ENA_INTR_DB_ENA             GENMASK(7, 0)
#define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\
	FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
#define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\
	FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)

/*      FDMA:FDMA:FDMA_INTR_ERR */
#define FDMA_INTR_ERR             __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)

/*      FDMA:FDMA:FDMA_ERRORS */
#define FDMA_ERRORS               __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)

/*      PTP:PTP_CFG:PTP_PIN_INTR */
#define PTP_PIN_INTR              __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4)

#define PTP_PIN_INTR_INTR_PTP                    GENMASK(7, 0)
#define PTP_PIN_INTR_INTR_PTP_SET(x)\
	FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x)
#define PTP_PIN_INTR_INTR_PTP_GET(x)\
	FIELD_GET(PTP_PIN_INTR_INTR_PTP, x)

/*      PTP:PTP_CFG:PTP_PIN_INTR_ENA */
#define PTP_PIN_INTR_ENA          __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4)

#define PTP_PIN_INTR_ENA_INTR_ENA                GENMASK(7, 0)
#define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\
	FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x)
#define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\
	FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x)

/*      PTP:PTP_CFG:PTP_DOM_CFG */
#define PTP_DOM_CFG               __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4)

#define PTP_DOM_CFG_ENA                          GENMASK(11, 9)
#define PTP_DOM_CFG_ENA_SET(x)\
	FIELD_PREP(PTP_DOM_CFG_ENA, x)
#define PTP_DOM_CFG_ENA_GET(x)\
	FIELD_GET(PTP_DOM_CFG_ENA, x)

#define PTP_DOM_CFG_CLKCFG_DIS                   GENMASK(2, 0)
#define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\
	FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x)
#define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\
	FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x)

/*      PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */
#define PTP_CLK_PER_CFG(g, r)     __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4)

/*      PTP:PTP_PINS:PTP_PIN_CFG */
#define PTP_PIN_CFG(g)            __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4)

#define PTP_PIN_CFG_PIN_ACTION                   GENMASK(29, 27)
#define PTP_PIN_CFG_PIN_ACTION_SET(x)\
	FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x)
#define PTP_PIN_CFG_PIN_ACTION_GET(x)\
	FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x)

#define PTP_PIN_CFG_PIN_SYNC                     GENMASK(26, 25)
#define PTP_PIN_CFG_PIN_SYNC_SET(x)\
	FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x)
#define PTP_PIN_CFG_PIN_SYNC_GET(x)\
	FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x)

#define PTP_PIN_CFG_PIN_SELECT                   GENMASK(23, 21)
#define PTP_PIN_CFG_PIN_SELECT_SET(x)\
	FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x)
#define PTP_PIN_CFG_PIN_SELECT_GET(x)\
	FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x)

#define PTP_PIN_CFG_PIN_DOM                      GENMASK(17, 16)
#define PTP_PIN_CFG_PIN_DOM_SET(x)\
	FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x)
#define PTP_PIN_CFG_PIN_DOM_GET(x)\
	FIELD_GET(PTP_PIN_CFG_PIN_DOM, x)

/*      PTP:PTP_PINS:PTP_TOD_SEC_MSB */
#define PTP_TOD_SEC_MSB(g)        __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4)

#define PTP_TOD_SEC_MSB_TOD_SEC_MSB              GENMASK(15, 0)
#define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\
	FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x)
#define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\
	FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x)

/*      PTP:PTP_PINS:PTP_TOD_SEC_LSB */
#define PTP_TOD_SEC_LSB(g)        __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4)

/*      PTP:PTP_PINS:PTP_TOD_NSEC */
#define PTP_TOD_NSEC(g)           __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4)

#define PTP_TOD_NSEC_TOD_NSEC                    GENMASK(29, 0)
#define PTP_TOD_NSEC_TOD_NSEC_SET(x)\
	FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x)
#define PTP_TOD_NSEC_TOD_NSEC_GET(x)\
	FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x)

/*      PTP:PTP_PINS:WF_HIGH_PERIOD */
#define PTP_WF_HIGH_PERIOD(g)     __REG(TARGET_PTP,\
					0, 1, 0, g, 8, 64, 24, 0, 1, 4)

#define PTP_WF_HIGH_PERIOD_PIN_WFH(x)            ((x) & GENMASK(29, 0))
#define PTP_WF_HIGH_PERIOD_PIN_WFH_M             GENMASK(29, 0)
#define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x)          ((x) & GENMASK(29, 0))

/*      PTP:PTP_PINS:WF_LOW_PERIOD */
#define PTP_WF_LOW_PERIOD(g)      __REG(TARGET_PTP,\
					0, 1, 0, g, 8, 64, 28, 0, 1, 4)

#define PTP_WF_LOW_PERIOD_PIN_WFL(x)             ((x) & GENMASK(29, 0))
#define PTP_WF_LOW_PERIOD_PIN_WFL_M              GENMASK(29, 0)
#define PTP_WF_LOW_PERIOD_PIN_WFL_X(x)           ((x) & GENMASK(29, 0))

/*      PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */
#define PTP_TWOSTEP_CTRL          __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4)

#define PTP_TWOSTEP_CTRL_NXT                     BIT(11)
#define PTP_TWOSTEP_CTRL_NXT_SET(x)\
	FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x)
#define PTP_TWOSTEP_CTRL_NXT_GET(x)\
	FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x)

#define PTP_TWOSTEP_CTRL_VLD                     BIT(10)
#define PTP_TWOSTEP_CTRL_VLD_SET(x)\
	FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x)
#define PTP_TWOSTEP_CTRL_VLD_GET(x)\
	FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x)

#define PTP_TWOSTEP_CTRL_STAMP_TX                BIT(9)
#define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
	FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x)
#define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
	FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x)

#define PTP_TWOSTEP_CTRL_STAMP_PORT              GENMASK(8, 1)
#define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
	FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
#define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
	FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x)

#define PTP_TWOSTEP_CTRL_OVFL                    BIT(0)
#define PTP_TWOSTEP_CTRL_OVFL_SET(x)\
	FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x)
#define PTP_TWOSTEP_CTRL_OVFL_GET(x)\
	FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x)

/*      PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */
#define PTP_TWOSTEP_STAMP         __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4)

#define PTP_TWOSTEP_STAMP_STAMP_NSEC             GENMASK(31, 2)
#define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\
	FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
#define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\
	FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x)

/*      DEVCPU_QS:XTR:XTR_GRP_CFG */
#define QS_XTR_GRP_CFG(r)         __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)

#define QS_XTR_GRP_CFG_MODE                      GENMASK(3, 2)
#define QS_XTR_GRP_CFG_MODE_SET(x)\
	FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
#define QS_XTR_GRP_CFG_MODE_GET(x)\
	FIELD_GET(QS_XTR_GRP_CFG_MODE, x)

#define QS_XTR_GRP_CFG_BYTE_SWAP                 BIT(0)
#define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
	FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
#define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
	FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)

/*      DEVCPU_QS:XTR:XTR_RD */
#define QS_XTR_RD(r)              __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)

/*      DEVCPU_QS:XTR:XTR_FLUSH */
#define QS_XTR_FLUSH              __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)

/*      DEVCPU_QS:XTR:XTR_DATA_PRESENT */
#define QS_XTR_DATA_PRESENT       __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)

/*      DEVCPU_QS:INJ:INJ_GRP_CFG */
#define QS_INJ_GRP_CFG(r)         __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)

#define QS_INJ_GRP_CFG_MODE                      GENMASK(3, 2)
#define QS_INJ_GRP_CFG_MODE_SET(x)\
	FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
#define QS_INJ_GRP_CFG_MODE_GET(x)\
	FIELD_GET(QS_INJ_GRP_CFG_MODE, x)

#define QS_INJ_GRP_CFG_BYTE_SWAP                 BIT(0)
#define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
	FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
#define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
	FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)

/*      DEVCPU_QS:INJ:INJ_WR */
#define QS_INJ_WR(r)              __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)

/*      DEVCPU_QS:INJ:INJ_CTRL */
#define QS_INJ_CTRL(r)            __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)

#define QS_INJ_CTRL_GAP_SIZE                     GENMASK(24, 21)
#define QS_INJ_CTRL_GAP_SIZE_SET(x)\
	FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
#define QS_INJ_CTRL_GAP_SIZE_GET(x)\
	FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)

#define QS_INJ_CTRL_EOF                          BIT(19)
#define QS_INJ_CTRL_EOF_SET(x)\
	FIELD_PREP(QS_INJ_CTRL_EOF, x)
#define QS_INJ_CTRL_EOF_GET(x)\
	FIELD_GET(QS_INJ_CTRL_EOF, x)

#define QS_INJ_CTRL_SOF                          BIT(18)
#define QS_INJ_CTRL_SOF_SET(x)\
	FIELD_PREP(QS_INJ_CTRL_SOF, x)
#define QS_INJ_CTRL_SOF_GET(x)\
	FIELD_GET(QS_INJ_CTRL_SOF, x)

#define QS_INJ_CTRL_VLD_BYTES                    GENMASK(17, 16)
#define QS_INJ_CTRL_VLD_BYTES_SET(x)\
	FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
#define QS_INJ_CTRL_VLD_BYTES_GET(x)\
	FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)

/*      DEVCPU_QS:INJ:INJ_STATUS */
#define QS_INJ_STATUS             __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)

#define QS_INJ_STATUS_WMARK_REACHED              GENMASK(5, 4)
#define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
	FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
#define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
	FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)

#define QS_INJ_STATUS_FIFO_RDY                   GENMASK(3, 2)
#define QS_INJ_STATUS_FIFO_RDY_SET(x)\
	FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
#define QS_INJ_STATUS_FIFO_RDY_GET(x)\
	FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)

/*      QSYS:SYSTEM:PORT_MODE */
#define QSYS_PORT_MODE(r)         __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4)

#define QSYS_PORT_MODE_DEQUEUE_DIS               BIT(1)
#define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\
	FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x)
#define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\
	FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x)

/*      QSYS:SYSTEM:SWITCH_PORT_MODE */
#define QSYS_SW_PORT_MODE(r)      __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4)

#define QSYS_SW_PORT_MODE_PORT_ENA               BIT(18)
#define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\
	FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x)
#define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\
	FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x)

#define QSYS_SW_PORT_MODE_SCH_NEXT_CFG           GENMASK(16, 14)
#define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\
	FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
#define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\
	FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)

#define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE      BIT(12)
#define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
	FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
#define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
	FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)

#define QSYS_SW_PORT_MODE_TX_PFC_ENA             GENMASK(11, 4)
#define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\
	FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
#define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\
	FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)

#define QSYS_SW_PORT_MODE_AGING_MODE             GENMASK(1, 0)
#define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\
	FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x)
#define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\
	FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x)

/*      QSYS:SYSTEM:SW_STATUS */
#define QSYS_SW_STATUS(r)         __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4)

#define QSYS_SW_STATUS_EQ_AVAIL                  GENMASK(7, 0)
#define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\
	FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x)
#define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\
	FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x)

/*      QSYS:SYSTEM:CPU_GROUP_MAP */
#define QSYS_CPU_GROUP_MAP        __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4)

/*      QSYS:RES_CTRL:RES_CFG */
#define QSYS_RES_CFG(g)           __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4)

/*      QSYS:HSCH:CIR_CFG */
#define QSYS_CIR_CFG(g)           __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4)

#define QSYS_CIR_CFG_CIR_RATE                    GENMASK(20, 6)
#define QSYS_CIR_CFG_CIR_RATE_SET(x)\
	FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x)
#define QSYS_CIR_CFG_CIR_RATE_GET(x)\
	FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x)

#define QSYS_CIR_CFG_CIR_BURST                   GENMASK(5, 0)
#define QSYS_CIR_CFG_CIR_BURST_SET(x)\
	FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x)
#define QSYS_CIR_CFG_CIR_BURST_GET(x)\
	FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x)

/*      QSYS:HSCH:SE_CFG */
#define QSYS_SE_CFG(g)            __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4)

#define QSYS_SE_CFG_SE_DWRR_CNT                  GENMASK(9, 6)
#define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\
	FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x)
#define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\
	FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x)

#define QSYS_SE_CFG_SE_RR_ENA                    BIT(5)
#define QSYS_SE_CFG_SE_RR_ENA_SET(x)\
	FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x)
#define QSYS_SE_CFG_SE_RR_ENA_GET(x)\
	FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x)

#define QSYS_SE_CFG_SE_AVB_ENA                   BIT(4)
#define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\
	FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x)
#define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\
	FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x)

#define QSYS_SE_CFG_SE_FRM_MODE                  GENMASK(3, 2)
#define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\
	FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x)
#define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\
	FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x)

#define QSYS_SE_DWRR_CFG(g, r)    __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4)

#define QSYS_SE_DWRR_CFG_DWRR_COST               GENMASK(4, 0)
#define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\
	FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x)
#define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\
	FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x)

/*      QSYS:TAS_CONFIG:TAS_CFG_CTRL */
#define QSYS_TAS_CFG_CTRL         __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4)

#define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX           GENMASK(27, 23)
#define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\
	FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x)
#define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\
	FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x)

#define QSYS_TAS_CFG_CTRL_LIST_NUM               GENMASK(22, 18)
#define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\
	FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x)
#define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\
	FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x)

#define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q        BIT(17)
#define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\
	FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x)
#define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\
	FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x)

#define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM          GENMASK(16, 5)
#define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\
	FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x)
#define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\
	FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x)

/*      QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */
#define QSYS_TAS_GS_CTRL          __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 4, 0, 1, 4)

#define QSYS_TAS_GS_CTRL_HSCH_POS                GENMASK(2, 0)
#define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\
	FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x)
#define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\
	FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x)

/*      QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */
#define QSYS_TAS_STM_CFG          __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 8, 0, 1, 4)

#define QSYS_TAS_STM_CFG_REVISIT_DLY             GENMASK(7, 0)
#define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\
	FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x)
#define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\
	FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x)

/*      QSYS:TAS_PROFILE_CFG:TAS_PROFILE_CONFIG */
#define QSYS_TAS_PROFILE_CFG(g)   __REG(TARGET_QSYS, 0, 1, 30720, g, 16, 64, 32, 0, 1, 4)

#define QSYS_TAS_PROFILE_CFG_PORT_NUM            GENMASK(21, 19)
#define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\
	FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x)
#define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\
	FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x)

#define QSYS_TAS_PROFILE_CFG_LINK_SPEED          GENMASK(18, 16)
#define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\
	FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x)
#define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\
	FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x)

/*      QSYS:TAS_LIST_CFG:TAS_BASE_TIME_NSEC */
#define QSYS_TAS_BT_NSEC          __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 0, 0, 1, 4)

#define QSYS_TAS_BT_NSEC_NSEC                    GENMASK(29, 0)
#define QSYS_TAS_BT_NSEC_NSEC_SET(x)\
	FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x)
#define QSYS_TAS_BT_NSEC_NSEC_GET(x)\
	FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x)

/*      QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_LSB */
#define QSYS_TAS_BT_SEC_LSB       __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 4, 0, 1, 4)

/*      QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_MSB */
#define QSYS_TAS_BT_SEC_MSB       __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 8, 0, 1, 4)

#define QSYS_TAS_BT_SEC_MSB_SEC_MSB              GENMASK(15, 0)
#define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\
	FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x)
#define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\
	FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x)

/*      QSYS:TAS_LIST_CFG:TAS_CYCLE_TIME_CFG */
#define QSYS_TAS_CT_CFG           __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 24, 0, 1, 4)

/*      QSYS:TAS_LIST_CFG:TAS_STARTUP_CFG */
#define QSYS_TAS_STARTUP_CFG      __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 28, 0, 1, 4)

#define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX        GENMASK(27, 23)
#define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\
	FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x)
#define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\
	FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x)

/*      QSYS:TAS_LIST_CFG:TAS_LIST_CFG */
#define QSYS_TAS_LIST_CFG         __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 32, 0, 1, 4)

#define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR         GENMASK(11, 0)
#define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\
	FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x)
#define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\
	FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x)

/*      QSYS:TAS_LIST_CFG:TAS_LIST_STATE */
#define QSYS_TAS_LST              __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4)

#define QSYS_TAS_LST_LIST_STATE                  GENMASK(2, 0)
#define QSYS_TAS_LST_LIST_STATE_SET(x)\
	FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x)
#define QSYS_TAS_LST_LIST_STATE_GET(x)\
	FIELD_GET(QSYS_TAS_LST_LIST_STATE, x)

/*      QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG */
#define QSYS_TAS_GCL_CT_CFG       __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 0, 0, 1, 4)

#define QSYS_TAS_GCL_CT_CFG_HSCH_POS             GENMASK(12, 10)
#define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\
	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x)
#define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\
	FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x)

#define QSYS_TAS_GCL_CT_CFG_GATE_STATE           GENMASK(9, 2)
#define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\
	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x)
#define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\
	FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x)

#define QSYS_TAS_GCL_CT_CFG_OP_TYPE              GENMASK(1, 0)
#define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\
	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x)
#define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\
	FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x)

/*      QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG2 */
#define QSYS_TAS_GCL_CT_CFG2      __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 4, 0, 1, 4)

#define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE        GENMASK(15, 12)
#define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\
	FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x)
#define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\
	FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x)

#define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL            GENMASK(11, 0)
#define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\
	FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x)
#define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\
	FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x)

/*      QSYS:TAS_GCL_CFG:TAS_GCL_TIME_CFG */
#define QSYS_TAS_GCL_TM_CFG       __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 8, 0, 1, 4)

/*      QSYS:HSCH_TAS_STATE:TAS_GATE_STATE */
#define QSYS_TAS_GATE_STATE       __REG(TARGET_QSYS, 0, 1, 28004, 0, 1, 4, 0, 0, 1, 4)

#define QSYS_TAS_GATE_STATE_TAS_GATE_STATE       GENMASK(7, 0)
#define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\
	FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x)
#define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\
	FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x)

/*      REW:PORT:PORT_VLAN_CFG */
#define REW_PORT_VLAN_CFG(g)      __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4)

#define REW_PORT_VLAN_CFG_PORT_TPID              GENMASK(31, 16)
#define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\
	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x)
#define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\
	FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x)

#define REW_PORT_VLAN_CFG_PORT_VID               GENMASK(11, 0)
#define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\
	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
#define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\
	FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)

/*      REW:PORT:TAG_CFG */
#define REW_TAG_CFG(g)            __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4)

#define REW_TAG_CFG_TAG_CFG                      GENMASK(8, 7)
#define REW_TAG_CFG_TAG_CFG_SET(x)\
	FIELD_PREP(REW_TAG_CFG_TAG_CFG, x)
#define REW_TAG_CFG_TAG_CFG_GET(x)\
	FIELD_GET(REW_TAG_CFG_TAG_CFG, x)

#define REW_TAG_CFG_TAG_TPID_CFG                 GENMASK(6, 5)
#define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\
	FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x)
#define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\
	FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x)

#define REW_TAG_CFG_TAG_PCP_CFG                  GENMASK(3, 2)
#define REW_TAG_CFG_TAG_PCP_CFG_SET(x)\
	FIELD_PREP(REW_TAG_CFG_TAG_PCP_CFG, x)
#define REW_TAG_CFG_TAG_PCP_CFG_GET(x)\
	FIELD_GET(REW_TAG_CFG_TAG_PCP_CFG, x)

#define REW_TAG_CFG_TAG_DEI_CFG                  GENMASK(1, 0)
#define REW_TAG_CFG_TAG_DEI_CFG_SET(x)\
	FIELD_PREP(REW_TAG_CFG_TAG_DEI_CFG, x)
#define REW_TAG_CFG_TAG_DEI_CFG_GET(x)\
	FIELD_GET(REW_TAG_CFG_TAG_DEI_CFG, x)

/*      REW:PORT:PORT_CFG */
#define REW_PORT_CFG(g)           __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4)

#define REW_PORT_CFG_ES0_EN                      BIT(4)
#define REW_PORT_CFG_ES0_EN_SET(x)\
	FIELD_PREP(REW_PORT_CFG_ES0_EN, x)
#define REW_PORT_CFG_ES0_EN_GET(x)\
	FIELD_GET(REW_PORT_CFG_ES0_EN, x)

#define REW_PORT_CFG_NO_REWRITE                  BIT(0)
#define REW_PORT_CFG_NO_REWRITE_SET(x)\
	FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x)
#define REW_PORT_CFG_NO_REWRITE_GET(x)\
	FIELD_GET(REW_PORT_CFG_NO_REWRITE, x)

/*      REW:PORT:DSCP_CFG */
#define REW_DSCP_CFG(g)           __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 12, 0, 1, 4)

#define REW_DSCP_CFG_DSCP_REWR_CFG               GENMASK(1, 0)
#define REW_DSCP_CFG_DSCP_REWR_CFG_SET(x)\
	FIELD_PREP(REW_DSCP_CFG_DSCP_REWR_CFG, x)
#define REW_DSCP_CFG_DSCP_REWR_CFG_GET(x)\
	FIELD_GET(REW_DSCP_CFG_DSCP_REWR_CFG, x)

/*      REW:PORT:PCP_DEI_QOS_MAP_CFG */
#define REW_PCP_DEI_CFG(g, r)     __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 16, r, 16, 4)

#define REW_PCP_DEI_CFG_DEI_QOS_VAL              BIT(3)
#define REW_PCP_DEI_CFG_DEI_QOS_VAL_SET(x)\
	FIELD_PREP(REW_PCP_DEI_CFG_DEI_QOS_VAL, x)
#define REW_PCP_DEI_CFG_DEI_QOS_VAL_GET(x)\
	FIELD_GET(REW_PCP_DEI_CFG_DEI_QOS_VAL, x)

#define REW_PCP_DEI_CFG_PCP_QOS_VAL              GENMASK(2, 0)
#define REW_PCP_DEI_CFG_PCP_QOS_VAL_SET(x)\
	FIELD_PREP(REW_PCP_DEI_CFG_PCP_QOS_VAL, x)
#define REW_PCP_DEI_CFG_PCP_QOS_VAL_GET(x)\
	FIELD_GET(REW_PCP_DEI_CFG_PCP_QOS_VAL, x)

/*      REW:COMMON:STAT_CFG */
#define REW_STAT_CFG              __REG(TARGET_REW, 0, 1, 3072, 0, 1, 528, 520, 0, 1, 4)

#define REW_STAT_CFG_STAT_MODE                   GENMASK(1, 0)
#define REW_STAT_CFG_STAT_MODE_SET(x)\
	FIELD_PREP(REW_STAT_CFG_STAT_MODE, x)
#define REW_STAT_CFG_STAT_MODE_GET(x)\
	FIELD_GET(REW_STAT_CFG_STAT_MODE, x)

/*      SYS:SYSTEM:RESET_CFG */
#define SYS_RESET_CFG             __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4)

#define SYS_RESET_CFG_CORE_ENA                   BIT(0)
#define SYS_RESET_CFG_CORE_ENA_SET(x)\
	FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x)
#define SYS_RESET_CFG_CORE_ENA_GET(x)\
	FIELD_GET(SYS_RESET_CFG_CORE_ENA, x)

/*      SYS:SYSTEM:PORT_MODE */
#define SYS_PORT_MODE(r)          __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4)

#define SYS_PORT_MODE_INCL_INJ_HDR               GENMASK(5, 4)
#define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\
	FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x)
#define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\
	FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x)

#define SYS_PORT_MODE_INCL_XTR_HDR               GENMASK(3, 2)
#define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\
	FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x)
#define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\
	FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x)

/*      SYS:SYSTEM:FRONT_PORT_MODE */
#define SYS_FRONT_PORT_MODE(r)    __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4)

#define SYS_FRONT_PORT_MODE_HDX_MODE             BIT(1)
#define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\
	FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x)
#define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\
	FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x)

/*      SYS:SYSTEM:FRM_AGING */
#define SYS_FRM_AGING             __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4)

#define SYS_FRM_AGING_AGE_TX_ENA                 BIT(20)
#define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\
	FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x)
#define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\
	FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x)

/*      SYS:SYSTEM:STAT_CFG */
#define SYS_STAT_CFG              __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4)

#define SYS_STAT_CFG_STAT_VIEW                   GENMASK(9, 0)
#define SYS_STAT_CFG_STAT_VIEW_SET(x)\
	FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x)
#define SYS_STAT_CFG_STAT_VIEW_GET(x)\
	FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x)

/*      SYS:PAUSE_CFG:PAUSE_CFG */
#define SYS_PAUSE_CFG(r)          __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4)

#define SYS_PAUSE_CFG_PAUSE_START                GENMASK(18, 10)
#define SYS_PAUSE_CFG_PAUSE_START_SET(x)\
	FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x)
#define SYS_PAUSE_CFG_PAUSE_START_GET(x)\
	FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x)

#define SYS_PAUSE_CFG_PAUSE_STOP                 GENMASK(9, 1)
#define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
	FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x)
#define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
	FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x)

#define SYS_PAUSE_CFG_PAUSE_ENA                  BIT(0)
#define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
	FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x)
#define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
	FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x)

/*      SYS:PAUSE_CFG:ATOP */
#define SYS_ATOP(r)               __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4)

/*      SYS:PAUSE_CFG:ATOP_TOT_CFG */
#define SYS_ATOP_TOT_CFG          __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4)

/*      SYS:PAUSE_CFG:MAC_FC_CFG */
#define SYS_MAC_FC_CFG(r)         __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4)

#define SYS_MAC_FC_CFG_FC_LINK_SPEED             GENMASK(27, 26)
#define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\
	FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
#define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\
	FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)

#define SYS_MAC_FC_CFG_FC_LATENCY_CFG            GENMASK(25, 20)
#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\
	FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\
	FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)

#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA            BIT(18)
#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\
	FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\
	FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)

#define SYS_MAC_FC_CFG_TX_FC_ENA                 BIT(17)
#define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\
	FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x)
#define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\
	FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x)

#define SYS_MAC_FC_CFG_RX_FC_ENA                 BIT(16)
#define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\
	FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x)
#define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\
	FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x)

#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG             GENMASK(15, 0)
#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\
	FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\
	FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)

/*      SYS:STAT:CNT */
#define SYS_CNT(g)                __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4)

/*      SYS:RAM_CTRL:RAM_INIT */
#define SYS_RAM_INIT              __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4)

#define SYS_RAM_INIT_RAM_INIT                    BIT(1)
#define SYS_RAM_INIT_RAM_INIT_SET(x)\
	FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x)
#define SYS_RAM_INIT_RAM_INIT_GET(x)\
	FIELD_GET(SYS_RAM_INIT_RAM_INIT, x)

/*      VCAP:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */
#define VCAP_UPDATE_CTRL(t)       __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 0, 0, 1, 4)

#define VCAP_UPDATE_CTRL_UPDATE_CMD              GENMASK(24, 22)
#define VCAP_UPDATE_CTRL_UPDATE_CMD_SET(x)\
	FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CMD, x)
#define VCAP_UPDATE_CTRL_UPDATE_CMD_GET(x)\
	FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CMD, x)

#define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS        BIT(21)
#define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(x)\
	FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_GET(x)\
	FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x)

#define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS       BIT(20)
#define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(x)\
	FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_GET(x)\
	FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x)

#define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS          BIT(19)
#define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(x)\
	FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x)
#define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_GET(x)\
	FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x)

#define VCAP_UPDATE_CTRL_UPDATE_ADDR             GENMASK(18, 3)
#define VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(x)\
	FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ADDR, x)
#define VCAP_UPDATE_CTRL_UPDATE_ADDR_GET(x)\
	FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ADDR, x)

#define VCAP_UPDATE_CTRL_UPDATE_SHOT             BIT(2)
#define VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(x)\
	FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_SHOT, x)
#define VCAP_UPDATE_CTRL_UPDATE_SHOT_GET(x)\
	FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_SHOT, x)

#define VCAP_UPDATE_CTRL_CLEAR_CACHE             BIT(1)
#define VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(x)\
	FIELD_PREP(VCAP_UPDATE_CTRL_CLEAR_CACHE, x)
#define VCAP_UPDATE_CTRL_CLEAR_CACHE_GET(x)\
	FIELD_GET(VCAP_UPDATE_CTRL_CLEAR_CACHE, x)

#define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN          BIT(0)
#define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_SET(x)\
	FIELD_PREP(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x)
#define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_GET(x)\
	FIELD_GET(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x)

/*      VCAP:VCAP_CORE_CFG:VCAP_MV_CFG */
#define VCAP_MV_CFG(t)            __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 4, 0, 1, 4)

#define VCAP_MV_CFG_MV_NUM_POS                   GENMASK(31, 16)
#define VCAP_MV_CFG_MV_NUM_POS_SET(x)\
	FIELD_PREP(VCAP_MV_CFG_MV_NUM_POS, x)
#define VCAP_MV_CFG_MV_NUM_POS_GET(x)\
	FIELD_GET(VCAP_MV_CFG_MV_NUM_POS, x)

#define VCAP_MV_CFG_MV_SIZE                      GENMASK(15, 0)
#define VCAP_MV_CFG_MV_SIZE_SET(x)\
	FIELD_PREP(VCAP_MV_CFG_MV_SIZE, x)
#define VCAP_MV_CFG_MV_SIZE_GET(x)\
	FIELD_GET(VCAP_MV_CFG_MV_SIZE, x)

/*      VCAP:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */
#define VCAP_ENTRY_DAT(t, r)      __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 0, r, 64, 4)

/*      VCAP:VCAP_CORE_CACHE:VCAP_MASK_DAT */
#define VCAP_MASK_DAT(t, r)       __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 256, r, 64, 4)

/*      VCAP:VCAP_CORE_CACHE:VCAP_ACTION_DAT */
#define VCAP_ACTION_DAT(t, r)     __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 512, r, 64, 4)

/*      VCAP:VCAP_CORE_CACHE:VCAP_CNT_DAT */
#define VCAP_CNT_DAT(t, r)        __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 768, r, 32, 4)

/*      VCAP:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */
#define VCAP_CNT_FW_DAT(t)        __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 896, 0, 1, 4)

/*      VCAP:VCAP_CORE_CACHE:VCAP_TG_DAT */
#define VCAP_TG_DAT(t)            __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 900, 0, 1, 4)

/*      VCAP:VCAP_CORE_MAP:VCAP_CORE_IDX */
#define VCAP_CORE_IDX(t)          __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 0, 0, 1, 4)

#define VCAP_CORE_IDX_CORE_IDX                   GENMASK(3, 0)
#define VCAP_CORE_IDX_CORE_IDX_SET(x)\
	FIELD_PREP(VCAP_CORE_IDX_CORE_IDX, x)
#define VCAP_CORE_IDX_CORE_IDX_GET(x)\
	FIELD_GET(VCAP_CORE_IDX_CORE_IDX, x)

/*      VCAP:VCAP_CORE_MAP:VCAP_CORE_MAP */
#define VCAP_CORE_MAP(t)          __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 4, 0, 1, 4)

#define VCAP_CORE_MAP_CORE_MAP                   GENMASK(2, 0)
#define VCAP_CORE_MAP_CORE_MAP_SET(x)\
	FIELD_PREP(VCAP_CORE_MAP_CORE_MAP, x)
#define VCAP_CORE_MAP_CORE_MAP_GET(x)\
	FIELD_GET(VCAP_CORE_MAP_CORE_MAP, x)

/*      VCAP:VCAP_CONST:VCAP_VER */
#define VCAP_VER(t)               __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 0, 0, 1, 4)

/*      VCAP:VCAP_CONST:ENTRY_WIDTH */
#define VCAP_ENTRY_WIDTH(t)       __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 4, 0, 1, 4)

/*      VCAP:VCAP_CONST:ENTRY_CNT */
#define VCAP_ENTRY_CNT(t)         __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 8, 0, 1, 4)

/*      VCAP:VCAP_CONST:ENTRY_SWCNT */
#define VCAP_ENTRY_SWCNT(t)       __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 12, 0, 1, 4)

/*      VCAP:VCAP_CONST:ENTRY_TG_WIDTH */
#define VCAP_ENTRY_TG_WIDTH(t)    __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 16, 0, 1, 4)

/*      VCAP:VCAP_CONST:ACTION_DEF_CNT */
#define VCAP_ACTION_DEF_CNT(t)    __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 20, 0, 1, 4)

/*      VCAP:VCAP_CONST:ACTION_WIDTH */
#define VCAP_ACTION_WIDTH(t)      __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 24, 0, 1, 4)

/*      VCAP:VCAP_CONST:CNT_WIDTH */
#define VCAP_CNT_WIDTH(t)         __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 28, 0, 1, 4)

/*      VCAP:VCAP_CONST:CORE_CNT */
#define VCAP_CORE_CNT(t)          __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 32, 0, 1, 4)

/*      VCAP:VCAP_CONST:IF_CNT */
#define VCAP_IF_CNT(t)            __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 36, 0, 1, 4)

#endif /* _LAN966X_REGS_H_ */