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| author | Andy Hu <andy.hu@starfivetech.com> | 2023-05-19 11:19:41 +0300 |
|---|---|---|
| committer | Andy Hu <andy.hu@starfivetech.com> | 2023-05-19 11:19:41 +0300 |
| commit | 68ad9c72a9cacd2e432b1d843e3902abbbb02e26 (patch) | |
| tree | e136fc3f2bbbcebfefb5dc7bc77bcbdd78d0cf23 | |
| parent | ea663c5401f9c0fadffe85d2b4ac394239e51e39 (diff) | |
| parent | 83e0510f2b9ab0fb46ee0e368d1fb96951a661cc (diff) | |
| download | linux-JH7110_VisionFive2_510_devel.tar.xz | |
Merge tag 'JH7110_510_SDK_v5.0.0' into vf2-510-develVF2_510_v3.0.0JH7110_VisionFive2_510_devel
update toolchain to gcc 12.2.0
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index efae173a6f92..bd6b4ec809c5 100755 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -66,7 +66,7 @@ }; cpu0: cpu@0 { - compatible = "sifive,u74-mc", "riscv"; + compatible = "sifive,s7", "riscv"; reg = <0>; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -81,7 +81,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imac"; + riscv,isa = "rv64imac_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "disabled"; @@ -109,7 +109,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "okay"; @@ -138,7 +138,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "okay"; @@ -167,7 +167,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "okay"; @@ -196,7 +196,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "okay"; |