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authorMichal Simek <michal.simek@amd.com>2024-01-09 16:32:39 +0300
committerRob Herring <robh@kernel.org>2024-01-12 00:50:56 +0300
commit22439cf4d1ca4861820b825f4f07958bdaed12d6 (patch)
tree133e59db365a38e4f463b050d1fae6bb5ff24b23 /Documentation/devicetree/bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml
parent36a7c96b3f265fd2bc5f518ae2fc60bed578da30 (diff)
downloadlinux-22439cf4d1ca4861820b825f4f07958bdaed12d6.tar.xz
dt-bindings: fpga: altera: Convert bridge bindings to yaml
Convert Altera's bridges to yaml with using fpga-bridge.yaml. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/07d646a6d82cc21b100e45ced7cae3ef05faa2cc.1704807147.git.michal.simek@amd.com Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml')
-rw-r--r--Documentation/devicetree/bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml49
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diff --git a/Documentation/devicetree/bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml b/Documentation/devicetree/bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml
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+++ b/Documentation/devicetree/bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera FPGA/HPS Bridge
+
+maintainers:
+ - Xu Yilun <yilun.xu@intel.com>
+
+allOf:
+ - $ref: fpga-bridge.yaml#
+
+properties:
+ compatible:
+ enum:
+ - altr,socfpga-lwhps2fpga-bridge
+ - altr,socfpga-hps2fpga-bridge
+ - altr,socfpga-fpga2hps-bridge
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/altr,rst-mgr.h>
+
+ fpga-bridge@ff400000 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ reg = <0xff400000 0x100000>;
+ bridge-enable = <0>;
+ clocks = <&l4_main_clk>;
+ resets = <&rst LWHPS2FPGA_RESET>;
+ };