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authorJamie Gibbons <jamie.gibbons@microchip.com>2024-03-27 15:24:37 +0300
committerBartosz Golaszewski <bartosz.golaszewski@linaro.org>2024-03-29 15:21:30 +0300
commit6e12a52c1459b791f27396a9b656b92aaa600065 (patch)
tree9992850252fd3bfb01f8029fa1c9d6b1f01f8918 /Documentation/devicetree/bindings/gpio
parent4cece764965020c22cff7665b18a012006359095 (diff)
downloadlinux-6e12a52c1459b791f27396a9b656b92aaa600065.tar.xz
dt-bindings: gpio: mpfs: add coreGPIO support
The GPIO controllers on PolarFire SoC were based on the "soft" IP CoreGPIO, but the inp/outp registers are at different offsets. Add compatible to allow for support of both sets of offsets. The soft core will not always have interrupts wired up, so only enforce them for the "hard" core on PolarFire SoC. Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/gpio')
-rw-r--r--Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml16
1 files changed, 13 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
index d481e78958a7..6884dacb2865 100644
--- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -14,6 +14,7 @@ properties:
items:
- enum:
- microchip,mpfs-gpio
+ - microchip,coregpio-rtl-v3
reg:
maxItems: 1
@@ -62,12 +63,21 @@ patternProperties:
- gpio-hog
- gpios
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,mpfs-gpio
+ then:
+ required:
+ - interrupts
+ - "#interrupt-cells"
+ - interrupt-controller
+
required:
- compatible
- reg
- - interrupts
- - "#interrupt-cells"
- - interrupt-controller
- "#gpio-cells"
- gpio-controller
- clocks