diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2023-06-16 01:50:15 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-23 00:23:53 +0300 |
| commit | 1ffe6ddc5c64f88b1ec2e250327defb5446a7904 (patch) | |
| tree | 2d469f396bc245a93655e3dc2b1db0753fcb3188 /Documentation/devicetree/bindings/riscv | |
| parent | 3c1b4758a9544cbaf38d052ad66a69618e920ceb (diff) | |
| download | linux-1ffe6ddc5c64f88b1ec2e250327defb5446a7904.tar.xz | |
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
To permit validation of cpu nodes, swap "additionalProperties: true"
out for "unevaluatedProperties: false".
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230615-viper-stoic-1ff8efd7d51d@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e89a10d9c06b..144da86718c1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -143,7 +143,7 @@ required: - riscv,isa - interrupt-controller -additionalProperties: true +unevaluatedProperties: false examples: - | |