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| author | Andrew Jones <ajones@ventanamicro.com> | 2023-02-24 19:26:26 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-15 07:26:03 +0300 |
| commit | ea20f117ab99d7c7653df656ddb795e51d9f7733 (patch) | |
| tree | e4590dbb37a042667c42cfac8fae077c98fef601 /Documentation/devicetree/bindings/riscv | |
| parent | 8b05e7d0408ac99e2f05f3673f2f249e9a9e10ec (diff) | |
| download | linux-ea20f117ab99d7c7653df656ddb795e51d9f7733.tar.xz | |
dt-bindings: riscv: Document cboz-block-size
The Zicboz operation (cbo.zero) operates on a block-size defined
for the cpu-core. While we already have the riscv,cbom-block-size
property, it only provides the block size for Zicbom operations.
Even though it's likely Zicboz and Zicbom will use the same size,
that's not required by the specification. Create another property
specifically for Zicboz.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230224162631.405473-4-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 001931d526ec..f24cf9601c6e 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -72,6 +72,11 @@ properties: description: The blocksize in bytes for the Zicbom cache operations. + riscv,cboz-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicboz cache operations. + riscv,isa: description: Identifies the specific RISC-V instruction set architecture |