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author | Trent Piepho <tpiepho@impinj.com> | 2019-05-22 21:43:22 +0300 |
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committer | David S. Miller <davem@davemloft.net> | 2019-05-23 03:40:17 +0300 |
commit | 13c83cf8af0dcc6103982b4dc0b70826f0b54f21 (patch) | |
tree | 66599156aea1d9922048e5a1bcc864afdd7d4212 /Documentation/s390 | |
parent | 980066e6d9642fa5854bed8e592b1a30ea885b76 (diff) | |
download | linux-13c83cf8af0dcc6103982b4dc0b70826f0b54f21.tar.xz |
net: phy: dp83867: Add ability to disable output clock
Generally, the output clock pin is only used for testing and only serves
as a source of RF noise after this. It could be used to daisy-chain
PHYs, but this is uncommon. Since the PHY can disable the output, make
doing so an option. I do this by adding another enumeration to the
allowed values of ti,clk-output-sel.
The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might
expect: to select the REF_CLK as the output. Rather it meant "keep
clock output setting as is", which, depending on PHY strapping, might
not be outputting REF_CLK.
Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output.
Omitting the property will leave the setting as is (which was the
previous behavior in this case).
Out of range values were silently converted into
DP83867_CLK_O_SEL_REF_CLK. Change this so they generate an error.
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/s390')
0 files changed, 0 insertions, 0 deletions