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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2024-01-24 15:29:36 +0300 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2024-04-12 18:11:49 +0300 |
| commit | 01fec70206d48891b76ee8a3a4bfbd331543c18a (patch) | |
| tree | dbde3f2b4ba9e56017e5f464a1333f04f5e26672 /Documentation | |
| parent | 78d212851f0e56b7d7083c4d5014aa7fa8b77e20 (diff) | |
| download | linux-01fec70206d48891b76ee8a3a4bfbd331543c18a.tar.xz | |
dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC
TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
The controller on J722S SoC is similar to the one present on TI's AM64
SoC, with the difference being that the controller on AM64 SoC supports
up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.
Update the bindings with a new compatible for J722S SoC.
Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3
Link: https://lore.kernel.org/linux-pci/20240124122936.816142-1-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 0b1f21570ed0..15a2658ceeef 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -23,6 +23,10 @@ properties: items: - const: ti,j7200-pcie-host - const: ti,j721e-pcie-host + - description: PCIe controller in J722S + items: + - const: ti,j722s-pcie-host + - const: ti,j721e-pcie-host reg: maxItems: 4 |