ARM: dts: Move .dts files to vendor sub-directories

The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
  been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
  company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>

1 files changed, 0 insertions, 370 deletions

diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
deleted file mode 100644
index 9f65403295ca..000000000000
--- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
+++ /dev/null
@@ -1,370 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/ {
-	soc {
-		pinctrl: pinctrl@40020000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x40020000 0x3000>;
-			interrupt-parent = <&exti>;
-			st,syscfg = <&syscfg 0x8>;
-
-			gpioa: gpio@40020000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x0 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
-				st,bank-name = "GPIOA";
-			};
-
-			gpiob: gpio@40020400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x400 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
-				st,bank-name = "GPIOB";
-			};
-
-			gpioc: gpio@40020800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x800 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
-				st,bank-name = "GPIOC";
-			};
-
-			gpiod: gpio@40020c00 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0xc00 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
-				st,bank-name = "GPIOD";
-			};
-
-			gpioe: gpio@40021000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x1000 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
-				st,bank-name = "GPIOE";
-			};
-
-			gpiof: gpio@40021400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x1400 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
-				st,bank-name = "GPIOF";
-			};
-
-			gpiog: gpio@40021800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x1800 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
-				st,bank-name = "GPIOG";
-			};
-
-			gpioh: gpio@40021c00 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x1c00 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
-				st,bank-name = "GPIOH";
-			};
-
-			gpioi: gpio@40022000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x2000 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
-				st,bank-name = "GPIOI";
-			};
-
-			gpioj: gpio@40022400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x2400 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
-				st,bank-name = "GPIOJ";
-			};
-
-			gpiok: gpio@40022800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				reg = <0x2800 0x400>;
-				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
-				st,bank-name = "GPIOK";
-			};
-
-			cec_pins_a: cec-0 {
-				pins {
-					pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
-					slew-rate = <0>;
-					drive-open-drain;
-					bias-disable;
-				};
-			};
-
-			usart1_pins_a: usart1-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <0>;
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
-					bias-disable;
-				};
-			};
-
-			usart1_pins_b: usart1-1 {
-				pins1 {
-					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <0>;
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
-					bias-disable;
-				};
-			};
-
-			i2c1_pins_b: i2c1-0 {
-				pins {
-					pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
-						 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
-					bias-disable;
-					drive-open-drain;
-					slew-rate = <0>;
-				};
-			};
-
-			usbotg_hs_pins_a: usbotg-hs-0 {
-				pins {
-					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
-						 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
-						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
-						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
-						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
-						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
-						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
-						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
-						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
-						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
-						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
-						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-			};
-
-			usbotg_hs_pins_b: usbotg-hs-1 {
-				pins {
-					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
-						 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
-						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
-						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
-						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
-						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
-						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
-						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
-						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
-						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
-						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
-						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-			};
-
-			usbotg_fs_pins_a: usbotg-fs-0 {
-				pins {
-					pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
-						 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
-						 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-			};
-
-			sdio_pins_a: sdio-pins-a-0 {
-				pins {
-					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
-						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
-						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
-						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
-						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
-						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-			};
-
-			sdio_pins_od_a: sdio-pins-od-a-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
-						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
-						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
-						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
-						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-
-				pins2 {
-					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
-					drive-open-drain;
-					slew-rate = <2>;
-				};
-			};
-
-			sdio_pins_b: sdio-pins-b-0 {
-				pins {
-					pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
-						 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
-						 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
-						 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
-						 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
-						 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-			};
-
-			sdio_pins_od_b: sdio-pins-od-b-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
-						 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
-						 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
-						 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
-						 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-
-				pins2 {
-					pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
-					drive-open-drain;
-					slew-rate = <2>;
-				};
-			};
-
-			can1_pins_a: can1-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
-					bias-pull-up;
-				};
-			};
-
-			can1_pins_b: can1-1 {
-				pins1 {
-					pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
-					bias-pull-up;
-				};
-			};
-
-			can1_pins_c: can1-2 {
-				pins1 {
-					pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
-					bias-pull-up;
-
-				};
-			};
-
-			can1_pins_d: can1-3 {
-				pins1 {
-					pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
-					bias-pull-up;
-
-				};
-			};
-
-			can2_pins_a: can2-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
-					bias-pull-up;
-				};
-			};
-
-			can2_pins_b: can2-1 {
-				pins1 {
-					pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
-					bias-pull-up;
-				};
-			};
-
-			can3_pins_a: can3-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
-					bias-pull-up;
-				};
-			};
-
-			can3_pins_b: can3-1 {
-				pins1 {
-					pinmux = <STM32_PINMUX('B', 4, AF11)>;  /* CAN3_TX */
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
-					bias-pull-up;
-				};
-			};
-		};
-	};
-};