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authorJiri Kosina <jkosina@suse.cz>2011-04-26 12:22:15 +0400
committerJiri Kosina <jkosina@suse.cz>2011-04-26 12:22:59 +0400
commit07f9479a40cc778bc1462ada11f95b01360ae4ff (patch)
tree0676cf38df3844004bb3ebfd99dfa67a4a8998f5 /arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
parent9d5e6bdb3013acfb311ab407eeca0b6a6a3dedbf (diff)
parentcd2e49e90f1cae7726c9a2c54488d881d7f1cd1c (diff)
downloadlinux-07f9479a40cc778bc1462ada11f95b01360ae4ff.tar.xz
Merge branch 'master' into for-next
Fast-forwarded to current state of Linus' tree as there are patches to be applied for files that didn't exist on the old branch.
Diffstat (limited to 'arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h')
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
index e01fc4607c91..0aeb6a6fe7f8 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -109,9 +109,9 @@
#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM)
/* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */
+#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interupt (For A0 only)) */
+#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */