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authorGregory CLEMENT <gregory.clement@free-electrons.com>2014-07-23 17:00:52 +0400
committerJason Cooper <jason@lakedaemon.net>2014-07-24 15:47:40 +0400
commite53b1fd432497942a0fdfd0e89c3d30241cb4d2c (patch)
tree5c091ae93b8ca9f2db67f354eed30f4a659f6eb4 /arch/arm/mach-mvebu/pmsu_ll.S
parent3b9e4b1441aedcb26079f690aa11f3f9f93e5182 (diff)
downloadlinux-e53b1fd432497942a0fdfd0e89c3d30241cb4d2c.tar.xz
ARM: mvebu: add cpuidle support for Armada 38x
Unlike the Armada XP and the Armada 370, this SoC uses a Cortex A9 core. Consequently, the procedure to enter the idle state is different: interaction with the SCU, not disabling snooping, etc. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-16-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/mach-mvebu/pmsu_ll.S')
-rw-r--r--arch/arm/mach-mvebu/pmsu_ll.S14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index 17d7f3b3976d..a945756cfb45 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -23,6 +23,20 @@ ARM_BE8(setend be ) @ go BE8 if entered LE
b cpu_resume
ENDPROC(armada_370_xp_cpu_resume)
+ENTRY(armada_38x_cpu_resume)
+ /* do we need it for Armada 38x*/
+ARM_BE8(setend be ) @ go BE8 if entered LE
+ bl v7_invalidate_l1
+ mrc p15, 4, r1, c15, c0 @ get SCU base address
+ orr r1, r1, #0x8 @ SCU CPU Power Status Register
+ mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
+ and r0, r0, #15
+ add r1, r1, r0
+ mov r0, #0x0
+ strb r0, [r1] @ switch SCU power state to Normal mode
+ b cpu_resume
+ENDPROC(armada_38x_cpu_resume)
+
.global mvebu_boot_wa_start
.global mvebu_boot_wa_end