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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 20:31:45 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 20:31:45 +0400
commit97b1007a2924aaa9126398623f6755a8c3c6a616 (patch)
treeb65c6edb631256e64bb3c72f083fa1be048de097 /arch/arm/mach-omap2
parentdfab34aa61a0f8c14a67d7b4c1dae28e57ba592d (diff)
parente0d20b69d3fa74a21ec363989612bddd58b930b8 (diff)
downloadlinux-97b1007a2924aaa9126398623f6755a8c3c6a616.tar.xz
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson: "This branch contains part 1 of the platform updates for 3.10. Among the highlights: - Support for the new Atmel Cortex-A5 based platforms (SAMA5D3) - New support for CSR SiRFatlas6 SoCs - A handful of updates for NVidia T114 (a.k.a. Tegra 4) - A bunch of updates for the shmobile platforms - A handful of updates for davinci - A few updates for Qualcomm MSM - Plus a handful of other patches, defconfig updates, etc." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (135 commits) ARM: tegra: pm: fix build error w/o PM_SLEEP ARM: davinci: ensure global variables are declared ARM: davinci: sram.c: fix incorrect type in assignment ARM: davinci: da8xx dt: make file local symbols static ARM: davinci: da8xx: add remoteproc support ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries ARM: socfpga: Add clock entries into device tree ARM: socfpga: Enable soft reset ARM: EXYNOS: replace cpumask by the corresponding macro ARM: EXYNOS: handle properly the return values ARM: EXYNOS: factor out the idle states ARM: OMAP4: Enable fix for Cortex-A9 erratas ARM: OMAP2+: Export SoC information to userspace ARM: OMAP2+: SoC name and revision unification ARM: OMAP2+: Move common part of late init into common function ARM: tegra: pm: remove duplicated include from pm.c ARM: davinci: da850: override mmc DT node device name ARM: davinci: da850: add mmc DT entries mmc: davinci_mmc: add DT support ARM: SAMSUNG: check processor type before cache restoration in resume ...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig3
-rw-r--r--arch/arm/mach-omap2/cclock2430_data.c4
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c10
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/common.h8
-rw-r--r--arch/arm/mach-omap2/devices.c149
-rw-r--r--arch/arm/mach-omap2/id.c95
-rw-r--r--arch/arm/mach-omap2/io.c34
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c36
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c81
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c92
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c172
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h4
15 files changed, 515 insertions, 179 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4dc34ae6a857..5c27c4747469 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,6 +15,7 @@ config ARCH_OMAP2PLUS
select OMAP_DM_TIMER
select PINCTRL
select PROC_DEVICETREE if PROC_FS
+ select SOC_BUS
select SPARSE_IRQ
select USE_OF
help
@@ -99,6 +100,8 @@ config ARCH_OMAP4
select PM_RUNTIME if CPU_IDLE
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select COMMON_CLK
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
config SOC_OMAP5
bool "TI OMAP5"
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index bda353b2f7d9..5e4b037bb24c 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -1978,9 +1978,11 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "des_ick", &des_ick),
CLK("omap-sham", "ick", &sha_ick),
- CLK("omap_rng", "ick", &rng_ick),
+ CLK(NULL, "sha_ick", &sha_ick),
+ CLK("omap_rng", "ick", &rng_ick),
CLK(NULL, "rng_ick", &rng_ick),
CLK("omap-aes", "ick", &aes_ick),
+ CLK(NULL, "aes_ick", &aes_ick),
CLK(NULL, "pka_ick", &pka_ick),
CLK(NULL, "usb_fck", &usb_fck),
CLK("musb-omap2430", "ick", &usbhs_ick),
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 332c6d3e55a9..6ebc7803bc3e 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -413,6 +413,14 @@ static struct clk smartreflex1_fck;
DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
+static struct clk sha0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
+DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
+
+static struct clk aes0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
+DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
+
/*
* Modules clock nodes
*
@@ -878,6 +886,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, "mmu_fck", &mmu_fck),
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
+ CLK(NULL, "sha0_fck", &sha0_fck),
+ CLK(NULL, "aes0_fck", &aes0_fck),
CLK(NULL, "timer1_fck", &timer1_fck),
CLK(NULL, "timer2_fck", &timer2_fck),
CLK(NULL, "timer3_fck", &timer3_fck),
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 438d13341e23..45cd26430d1f 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3471,8 +3471,10 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
CLK(NULL, "init_60m_fclk", &dummy_ck),
CLK(NULL, "gpt1_fck", &gpt1_fck),
+ CLK(NULL, "aes2_ick", &aes2_ick),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
CLK(NULL, "gpio1_dbck", &gpio1_dbck),
+ CLK(NULL, "sha12_ick", &sha12_ick),
CLK(NULL, "wdt2_fck", &wdt2_fck),
CLK("omap_wdt", "ick", &wdt2_ick),
CLK(NULL, "wdt2_ick", &wdt2_ick),
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 14522d077c88..df00e7580aa7 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -110,6 +110,14 @@ void am35xx_init_late(void);
void ti81xx_init_late(void);
int omap2_common_pm_late_init(void);
+#ifdef CONFIG_SOC_BUS
+void omap_soc_device_init(void);
+#else
+static inline void omap_soc_device_init(void)
+{
+}
+#endif
+
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
void omap2xxx_restart(char mode, const char *cmd);
#else
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 1ec7f0597710..4269fc145698 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -504,140 +504,31 @@ static void omap_init_rng(void)
WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
}
-#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_sham_resources[] = {
- {
- .start = OMAP24XX_SEC_SHA1MD5_BASE,
- .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 51 + OMAP_INTC_START,
- .flags = IORESOURCE_IRQ,
- }
-};
-static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
-#else
-#define omap2_sham_resources NULL
-#define omap2_sham_resources_sz 0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_sham_resources[] = {
- {
- .start = OMAP34XX_SEC_SHA1MD5_BASE,
- .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 49 + OMAP_INTC_START,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = OMAP34XX_DMA_SHA1MD5_RX,
- .flags = IORESOURCE_DMA,
- }
-};
-static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
-#else
-#define omap3_sham_resources NULL
-#define omap3_sham_resources_sz 0
-#endif
-
-static struct platform_device sham_device = {
- .name = "omap-sham",
- .id = -1,
-};
-
-static void omap_init_sham(void)
+static void __init omap_init_sham(void)
{
- if (cpu_is_omap24xx()) {
- sham_device.resource = omap2_sham_resources;
- sham_device.num_resources = omap2_sham_resources_sz;
- } else if (cpu_is_omap34xx()) {
- sham_device.resource = omap3_sham_resources;
- sham_device.num_resources = omap3_sham_resources_sz;
- } else {
- pr_err("%s: platform not supported\n", __func__);
- return;
- }
- platform_device_register(&sham_device);
-}
-#else
-static inline void omap_init_sham(void) { }
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_aes_resources[] = {
- {
- .start = OMAP24XX_SEC_AES_BASE,
- .end = OMAP24XX_SEC_AES_BASE + 0x4C,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP24XX_DMA_AES_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = OMAP24XX_DMA_AES_RX,
- .flags = IORESOURCE_DMA,
- }
-};
-static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
-#else
-#define omap2_aes_resources NULL
-#define omap2_aes_resources_sz 0
-#endif
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_aes_resources[] = {
- {
- .start = OMAP34XX_SEC_AES_BASE,
- .end = OMAP34XX_SEC_AES_BASE + 0x4C,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP34XX_DMA_AES2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = OMAP34XX_DMA_AES2_RX,
- .flags = IORESOURCE_DMA,
- }
-};
-static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
-#else
-#define omap3_aes_resources NULL
-#define omap3_aes_resources_sz 0
-#endif
+ oh = omap_hwmod_lookup("sham");
+ if (!oh)
+ return;
-static struct platform_device aes_device = {
- .name = "omap-aes",
- .id = -1,
-};
+ pdev = omap_device_build("omap-sham", -1, oh, NULL, 0);
+ WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
+}
-static void omap_init_aes(void)
+static void __init omap_init_aes(void)
{
- if (cpu_is_omap24xx()) {
- aes_device.resource = omap2_aes_resources;
- aes_device.num_resources = omap2_aes_resources_sz;
- } else if (cpu_is_omap34xx()) {
- aes_device.resource = omap3_aes_resources;
- aes_device.num_resources = omap3_aes_resources_sz;
- } else {
- pr_err("%s: platform not supported\n", __func__);
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
+
+ oh = omap_hwmod_lookup("aes");
+ if (!oh)
return;
- }
- platform_device_register(&aes_device);
-}
-#else
-static inline void omap_init_aes(void) { }
-#endif
+ pdev = omap_device_build("omap-aes", -1, oh, NULL, 0);
+ WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
+}
/*-------------------------------------------------------------------------*/
@@ -764,11 +655,11 @@ static int __init omap2_init_devices(void)
omap_init_dmic();
omap_init_mcpdm();
omap_init_mcspi();
+ omap_init_sham();
+ omap_init_aes();
}
omap_init_sti();
omap_init_rng();
- omap_init_sham();
- omap_init_aes();
omap_init_vout();
omap_init_ocp2scp();
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index ff0bc9e51aa7..2fb17caa8683 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -18,6 +18,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/slab.h>
+
+#ifdef CONFIG_SOC_BUS
+#include <linux/sys_soc.h>
+#endif
#include <asm/cputype.h>
@@ -31,8 +36,11 @@
#define OMAP4_SILICON_TYPE_STANDARD 0x01
#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
+#define OMAP_SOC_MAX_NAME_LENGTH 16
+
static unsigned int omap_revision;
-static const char *cpu_rev;
+static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
+static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
u32 omap_features;
unsigned int omap_rev(void)
@@ -169,9 +177,12 @@ void __init omap2xxx_check_revision(void)
j = i;
}
- pr_info("OMAP%04x", omap_rev() >> 16);
+ sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+ sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
+
+ pr_info("%s", soc_name);
if ((omap_rev() >> 8) & 0x0f)
- pr_info("ES%x", (omap_rev() >> 12) & 0xf);
+ pr_info("%s", soc_rev);
pr_info("\n");
}
@@ -211,8 +222,10 @@ static void __init omap3_cpuinfo(void)
cpu_name = "OMAP3503";
}
+ sprintf(soc_name, "%s", cpu_name);
+
/* Print verbose information */
- pr_info("%s ES%s (", cpu_name, cpu_rev);
+ pr_info("%s %s (", soc_name, soc_rev);
OMAP3_SHOW_FEATURE(l2cache);
OMAP3_SHOW_FEATURE(iva);
@@ -291,6 +304,7 @@ void __init ti81xx_check_features(void)
void __init omap3xxx_check_revision(void)
{
+ const char *cpu_rev;
u32 cpuid, idcode;
u16 hawkeye;
u8 rev;
@@ -438,6 +452,7 @@ void __init omap3xxx_check_revision(void)
cpu_rev = "1.2";
pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
}
+ sprintf(soc_rev, "ES%s", cpu_rev);
}
void __init omap4xxx_check_revision(void)
@@ -512,8 +527,10 @@ void __init omap4xxx_check_revision(void)
omap_revision = OMAP4430_REV_ES2_3;
}
- pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
- ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+ sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+ sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
+ (omap_rev() >> 8) & 0xf);
+ pr_info("%s %s\n", soc_name, soc_rev);
}
void __init omap5xxx_check_revision(void)
@@ -553,8 +570,10 @@ void __init omap5xxx_check_revision(void)
omap_revision = OMAP5430_REV_ES2_0;
}
- pr_info("OMAP%04x ES%d.0\n",
- omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+ sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+ sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
+
+ pr_info("%s %s\n", soc_name, soc_rev);
}
/*
@@ -575,3 +594,63 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
else
tap_prod_id = 0x0208;
}
+
+#ifdef CONFIG_SOC_BUS
+
+static const char const *omap_types[] = {
+ [OMAP2_DEVICE_TYPE_TEST] = "TST",
+ [OMAP2_DEVICE_TYPE_EMU] = "EMU",
+ [OMAP2_DEVICE_TYPE_SEC] = "HS",
+ [OMAP2_DEVICE_TYPE_GP] = "GP",
+ [OMAP2_DEVICE_TYPE_BAD] = "BAD",
+};
+
+static const char * __init omap_get_family(void)
+{
+ if (cpu_is_omap24xx())
+ return kasprintf(GFP_KERNEL, "OMAP2");
+ else if (cpu_is_omap34xx())
+ return kasprintf(GFP_KERNEL, "OMAP3");
+ else if (cpu_is_omap44xx())
+ return kasprintf(GFP_KERNEL, "OMAP4");
+ else if (soc_is_omap54xx())
+ return kasprintf(GFP_KERNEL, "OMAP5");
+ else
+ return kasprintf(GFP_KERNEL, "Unknown");
+}
+
+static ssize_t omap_get_type(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%s\n", omap_types[omap_type()]);
+}
+
+static struct device_attribute omap_soc_attr =
+ __ATTR(type, S_IRUGO, omap_get_type, NULL);
+
+void __init omap_soc_device_init(void)
+{
+ struct device *parent;
+ struct soc_device *soc_dev;
+ struct soc_device_attribute *soc_dev_attr;
+
+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return;
+
+ soc_dev_attr->machine = soc_name;
+ soc_dev_attr->family = omap_get_family();
+ soc_dev_attr->revision = soc_rev;
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR_OR_NULL(soc_dev)) {
+ kfree(soc_dev_attr);
+ return;
+ }
+
+ parent = soc_device_to_device(soc_dev);
+ if (!IS_ERR_OR_NULL(parent))
+ device_create_file(parent, &omap_soc_attr);
+}
+#endif /* CONFIG_SOC_BUS */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e210fa830f8d..09abf99e9e57 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -394,6 +394,13 @@ static void __init omap_hwmod_init_postsetup(void)
omap_pm_if_early_init();
}
+static void __init omap_common_late_init(void)
+{
+ omap_mux_late_init();
+ omap2_common_pm_late_init();
+ omap_soc_device_init();
+}
+
#ifdef CONFIG_SOC_OMAP2420
void __init omap2420_init_early(void)
{
@@ -417,8 +424,7 @@ void __init omap2420_init_early(void)
void __init omap2420_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap2_pm_init();
omap2_clk_enable_autoidle_all();
}
@@ -447,8 +453,7 @@ void __init omap2430_init_early(void)
void __init omap2430_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap2_pm_init();
omap2_clk_enable_autoidle_all();
}
@@ -520,48 +525,42 @@ void __init ti81xx_init_early(void)
void __init omap3_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
void __init omap3430_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
void __init omap35xx_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
void __init omap3630_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
void __init am35xx_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
void __init ti81xx_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap3_pm_init();
omap2_clk_enable_autoidle_all();
}
@@ -613,8 +612,7 @@ void __init omap4430_init_early(void)
void __init omap4430_init_late(void)
{
- omap_mux_late_init();
- omap2_common_pm_late_init();
+ omap_common_late_init();
omap4_pm_init();
omap2_clk_enable_autoidle_all();
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 6a764af6c6d3..5137cc84b504 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -610,6 +610,8 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
&omap2420_l4_core__mcbsp2,
&omap2420_l4_core__msdi1,
&omap2xxx_l4_core__rng,
+ &omap2xxx_l4_core__sham,
+ &omap2xxx_l4_core__aes,
&omap2420_l4_core__hdq1w,
&omap2420_l4_wkup__counter_32k,
&omap2420_l3__gpmc,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index d2d3840557c3..4ce999ee3ee9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -963,6 +963,8 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
&omap2430_l4_core__mcbsp5,
&omap2430_l4_core__hdq1w,
&omap2xxx_l4_core__rng,
+ &omap2xxx_l4_core__sham,
+ &omap2xxx_l4_core__aes,
&omap2430_l4_wkup__counter_32k,
&omap2430_l3__gpmc,
NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 47901a5e76de..5fd40d4a989e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -138,6 +138,24 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
{ }
};
+static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
+ {
+ .pa_start = 0x480a4000,
+ .pa_end = 0x480a4000 + 0x64 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
+ {
+ .pa_start = 0x480a6000,
+ .pa_end = 0x480a6000 + 0x50 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
/*
* Common interconnect data
*/
@@ -389,3 +407,21 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
.addr = omap2_rng_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+
+/* l4 core -> sham interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_sham_hwmod,
+ .clk = "sha_ick",
+ .addr = omap2xxx_sham_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> aes interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_aes_hwmod,
+ .clk = "aes_ick",
+ .addr = omap2xxx_aes_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index e596117004d4..c8c64b3e1acc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -864,3 +864,84 @@ struct omap_hwmod omap2xxx_rng_hwmod = {
.flags = HWMOD_INIT_NO_RESET,
.class = &omap2_rng_hwmod_class,
};
+
+/* SHAM */
+
+static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
+ .rev_offs = 0x5c,
+ .sysc_offs = 0x60,
+ .syss_offs = 0x64,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_sham_class = {
+ .name = "sham",
+ .sysc = &omap2_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
+ { .irq = 51 + OMAP_INTC_START, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
+ { .name = "rx", .dma_req = 13 },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_sham_hwmod = {
+ .name = "sham",
+ .mpu_irqs = omap2_sham_mpu_irqs,
+ .sdma_reqs = omap2_sham_sdma_chs,
+ .main_clk = "l4_ck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 4,
+ .module_bit = OMAP24XX_EN_SHA_SHIFT,
+ .idlest_reg_id = 4,
+ .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
+ },
+ },
+ .class = &omap2xxx_sham_class,
+};
+
+/* AES */
+
+static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
+ .rev_offs = 0x44,
+ .sysc_offs = 0x48,
+ .syss_offs = 0x4c,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_aes_class = {
+ .name = "aes",
+ .sysc = &omap2_aes_sysc,
+};
+
+static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
+ { .name = "tx", .dma_req = 9 },
+ { .name = "rx", .dma_req = 10 },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_aes_hwmod = {
+ .name = "aes",
+ .sdma_reqs = omap2_aes_sdma_chs,
+ .main_clk = "l4_ck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 4,
+ .module_bit = OMAP24XX_EN_AES_SHIFT,
+ .idlest_reg_id = 4,
+ .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
+ },
+ },
+ .class = &omap2xxx_aes_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 31bea1ce3de1..01d8f324450a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -418,8 +418,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
* - clkdiv32k
* - debugss
* - ocp watch point
- * - aes0
- * - sha0
*/
#if 0
/*
@@ -500,25 +498,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = {
},
},
};
+#endif
/*
- * 'aes' class
+ * 'aes0' class
*/
-static struct omap_hwmod_class am33xx_aes_hwmod_class = {
- .name = "aes",
+static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
+ .rev_offs = 0x80,
+ .sysc_offs = 0x84,
+ .syss_offs = 0x88,
+ .sysc_flags = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
+ .name = "aes0",
+ .sysc = &am33xx_aes0_sysc,
};
static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
- { .irq = 102 + OMAP_INTC_START, },
+ { .irq = 103 + OMAP_INTC_START, },
{ .irq = -1 },
};
+static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
+ { .name = "tx", .dma_req = 6, },
+ { .name = "rx", .dma_req = 5, },
+ { .dma_req = -1 }
+};
+
static struct omap_hwmod am33xx_aes0_hwmod = {
- .name = "aes0",
- .class = &am33xx_aes_hwmod_class,
+ .name = "aes",
+ .class = &am33xx_aes0_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_aes0_irqs,
- .main_clk = "l3_gclk",
+ .sdma_reqs = am33xx_aes0_edma_reqs,
+ .main_clk = "aes0_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
@@ -527,21 +541,35 @@ static struct omap_hwmod am33xx_aes0_hwmod = {
},
};
-/* sha0 */
+/* sha0 HIB2 (the 'P' (public) device) */
+static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
+ .rev_offs = 0x100,
+ .sysc_offs = 0x110,
+ .syss_offs = 0x114,
+ .sysc_flags = SYSS_HAS_RESET_STATUS,
+};
+
static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
.name = "sha0",
+ .sysc = &am33xx_sha0_sysc,
};
static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
- { .irq = 108 + OMAP_INTC_START, },
+ { .irq = 109 + OMAP_INTC_START, },
{ .irq = -1 },
};
+static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
+ { .name = "rx", .dma_req = 36, },
+ { .dma_req = -1 }
+};
+
static struct omap_hwmod am33xx_sha0_hwmod = {
- .name = "sha0",
+ .name = "sham",
.class = &am33xx_sha0_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_sha0_irqs,
+ .sdma_reqs = am33xx_sha0_edma_reqs,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
@@ -551,8 +579,6 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
},
};
-#endif
-
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
@@ -3449,6 +3475,42 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l3 main -> sha0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
+ {
+ .pa_start = 0x53100000,
+ .pa_end = 0x53100000 + SZ_512 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_sha0_hwmod,
+ .clk = "sha0_fck",
+ .addr = am33xx_sha0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> AES0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
+ {
+ .pa_start = 0x53500000,
+ .pa_end = 0x53500000 + SZ_1M - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_aes0_hwmod,
+ .clk = "aes0_fck",
+ .addr = am33xx_aes0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif,
@@ -3529,6 +3591,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,
+ &am33xx_l3_main__sha0,
+ &am33xx_l3_main__aes0,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5112d04e7b79..4083606ea1da 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3550,6 +3550,132 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
+static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
+ .sidle_shift = 4,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
+ .rev_offs = 0x5c,
+ .sysc_offs = 0x60,
+ .syss_offs = 0x64,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap3_sham_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_sham_class = {
+ .name = "sham",
+ .sysc = &omap3_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
+ { .irq = 49 + OMAP_INTC_START, },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_sham_hwmod = {
+ .name = "sham",
+ .mpu_irqs = omap3_sham_mpu_irqs,
+ .sdma_reqs = omap3_sham_sdma_reqs,
+ .main_clk = "sha12_ick",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_SHA12_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
+ },
+ },
+ .class = &omap3xxx_sham_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
+ {
+ .pa_start = 0x480c3000,
+ .pa_end = 0x480c3000 + 0x64 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_sham_hwmod,
+ .clk = "sha12_ick",
+ .addr = omap3xxx_sham_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> AES */
+static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
+ .sidle_shift = 6,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
+ .rev_offs = 0x44,
+ .sysc_offs = 0x48,
+ .syss_offs = 0x4c,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap3xxx_aes_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_aes_class = {
+ .name = "aes",
+ .sysc = &omap3_aes_sysc,
+};
+
+static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
+ { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_aes_hwmod = {
+ .name = "aes",
+ .sdma_reqs = omap3_aes_sdma_reqs,
+ .main_clk = "aes2_ick",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_AES2_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
+ },
+ },
+ .class = &omap3xxx_aes_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
+ {
+ .pa_start = 0x480c5000,
+ .pa_end = 0x480c5000 + 0x50 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_aes_hwmod,
+ .clk = "aes2_ick",
+ .addr = omap3xxx_aes_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l3_main__l4_core,
&omap3xxx_l3_main__l4_per,
@@ -3601,8 +3727,32 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
};
/* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
+static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12,
+ &omap3xxx_l4_core__sham,
+ &omap3xxx_l4_core__aes,
+ NULL
+};
+
+static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l4_sec__timer12,
+ &omap3xxx_l4_core__sham,
+ &omap3xxx_l4_core__aes,
+ NULL
+};
+
+static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
+ &omap3xxx_l4_sec__timer12,
+ /*
+ * Apparently the SHA/MD5 and AES accelerator IP blocks are
+ * only present on some AM35xx chips, and no one knows which
+ * ones. See
+ * http://www.spinics.net/lists/arm-kernel/msg215466.html So
+ * if you need these IP blocks on an AM35xx, try uncommenting
+ * the following lines.
+ */
+ /* &omap3xxx_l4_core__sham, */
+ /* &omap3xxx_l4_core__aes, */
NULL
};
@@ -3709,7 +3859,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
int __init omap3xxx_hwmod_init(void)
{
int r;
- struct omap_hwmod_ocp_if **h = NULL;
+ struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
unsigned int rev;
omap_hwmod_init();
@@ -3719,13 +3869,6 @@ int __init omap3xxx_hwmod_init(void)
if (r < 0)
return r;
- /* Register GP-only hwmod links. */
- if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
- r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
- if (r < 0)
- return r;
- }
-
rev = omap_rev();
/*
@@ -3737,11 +3880,14 @@ int __init omap3xxx_hwmod_init(void)
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
h = omap34xx_hwmod_ocp_ifs;
+ h_gp = omap34xx_gp_hwmod_ocp_ifs;
} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
h = am35xx_hwmod_ocp_ifs;
+ h_gp = am35xx_gp_hwmod_ocp_ifs;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
h = omap36xx_hwmod_ocp_ifs;
+ h_gp = omap36xx_gp_hwmod_ocp_ifs;
} else {
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
return -EINVAL;
@@ -3751,6 +3897,14 @@ int __init omap3xxx_hwmod_init(void)
if (r < 0)
return r;
+ /* Register GP-only hwmod links. */
+ if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
+ r = omap_hwmod_register_links(h_gp);
+ if (r < 0)
+ return r;
+ }
+
+
/*
* Register hwmod links specific to certain ES levels of a
* particular family of silicon (e.g., 34xx ES1.0)
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index cfcce299177c..6e04ff7065e1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -78,6 +78,8 @@ extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
extern struct omap_hwmod omap2xxx_gpmc_hwmod;
extern struct omap_hwmod omap2xxx_rng_hwmod;
+extern struct omap_hwmod omap2xxx_sham_hwmod;
+extern struct omap_hwmod omap2xxx_aes_hwmod;
/* Common interface data across OMAP2xxx */
extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -105,6 +107,8 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
/* Common IP block data */
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];