diff options
| author | Linu Cherian <lcherian@marvell.com> | 2022-03-07 17:30:14 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-03-08 00:45:02 +0300 |
| commit | 24a147bcef8ca039cb75d6d4b68c7cc339b11178 (patch) | |
| tree | 37b2fa86a84d07b495566edff338bd873b0d4c0c /arch/arm64/Kconfig | |
| parent | dfd42facf1e4ada021b939b4e19c935dcdd55566 (diff) | |
| download | linux-24a147bcef8ca039cb75d6d4b68c7cc339b11178.tar.xz | |
irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
When a IAR register read races with a GIC interrupt RELEASE event,
GIC-CPU interface could wrongly return a valid INTID to the CPU
for an interrupt that is already released(non activated) instead of 0x3ff.
As a side effect, an interrupt handler could run twice, once with
interrupt priority and then with idle priority.
As a workaround, gic_read_iar is updated so that it will return a
valid interrupt ID only if there is a change in the active priority list
after the IAR read on all the affected Silicons.
Since there are silicon variants where both 23154 and 38545 are applicable,
workaround for erratum 23154 has been extended to address both of them.
Signed-off-by: Linu Cherian <lcherian@marvell.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220307143014.22758-1-lcherian@marvell.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/Kconfig')
| -rw-r--r-- | arch/arm64/Kconfig | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index cbcd42decb2a..b154aa98c43a 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -890,13 +890,17 @@ config CAVIUM_ERRATUM_23144 If unsure, say Y. config CAVIUM_ERRATUM_23154 - bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" + bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" default y help - The gicv3 of ThunderX requires a modified version for + The ThunderX GICv3 implementation requires a modified version for reading the IAR status to ensure data synchronization (access to icc_iar1_el1 is not sync'ed before and after). + It also suffers from erratum 38545 (also present on Marvell's + OcteonTX and OcteonTX2), resulting in deactivated interrupts being + spuriously presented to the CPU interface. + If unsure, say Y. config CAVIUM_ERRATUM_27456 |