Merge tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC DT updates from Arnd Bergmann:
 "As usual, there are many patches addressing minor issues in existing
  DTS files, such as DTC warnings, or adding support for additional
  peripherals.

  There are three added SoCs in existing product families:

   - Amazon:

     Alpine v3 is a 16-core Cortex-A72 SoC from Amazon's Annapurna Labs,
     otherwise known as AL73400 or first-generation Graviton, and
     following the already supported Cortex-A1`5 and Cortex-A57 based
     Alpine chips. This one is added together with the official
     Evaluation platform.

   - Qualcomm:

     The Snapdragon SDM630 platform is a family of mid-range mobile
     phone chips from 2017 based on Cortex-A53 or Kryo 260 CPUs. A total
     of five end-user products are added based on these, all Android
     phones from Sony: Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra.

   - Renesas:

     RZ/G2H (r8a774e1) is currently the top model in the Renesas RZ/G
     family, and apparently closely related to the RZ/G2N and RZ/G2M
     models we already support but has a faster GPU and additional
     on-chip peripherals. It is added along with the HopeRun HiHope
     RZ/G2H development board

  A small number of new boards for already supported SoCs also debut:

   - Allwinner sunxi:

     Only one new machine, revision v1.2 of the Pine64 PinePhone
     (non-Android) smartphone, containing minor changes compared to
     earlier versions.

   - Amlogic Meson:

     WeTek Core2 is an Amlogic S912 (GXM) based Set-top-box

   - Aspeed:

     EthanolX is AMD's EPYC data center rerence platform, using an
     ASpeed AST2600 baseboard management controller.

   - Mediatek:

     Lenovo IdeaPad Duet 10.1" (kukui/krane) is a new Chromebook based
     on the MT8183 (Helio P60t) SoC.

   - Nvidia Tegra:

     ASUS Google Nexus 7 and Acer Iconia Tab A500 are two Android
     tablets from around 2012 using Tegra 3 and Tegra 2, respectively.
     Thanks to PostmarketOS, these can now run mainline kernels and
     become useful again.

     The Jetson Xavier NX Developer Kit uses a SoM and carrier board for
     the Tegra194, their latest 64-bit chip based on Carmel CPU cores
     and Volta graphics.

   - NXP i.MX:

     Five new boards based on the 32-bit i.MX6 series are added: The
     MYiR MYS-6ULX single-board computer, and four different models of
     industrial computers from Protonic.

   - Qualcomm:

     MikroTik RouterBoard 3011 is a rackmounted router based on the
     32-bit IPQ8064 networking SoC

     Three older phones get added, the Snapdragon 808 (msm8992) based
     Xiaomi Libra (Mi 4C) and Microsoft Lumia 950, originally running
     Windows Phone, and the Snapdragon 810 (msm8994) based Sony Xperia
     Z5.

   - Renesas:

     In addition to the HiHope RZ/G2H board mentioned above, we gain
     support for board versions 3.0 and 4.0 of the earlier RZ/G2M and
     RZ/G2N reference boards. Beacon EmbeddedWorks adds another
     SoM+Carrier development board for RZ/G2M.

   - Rockchips:

     Radxa Rock Pi N8 development board and the VMARC RK3288 SoM it is
     based on, using the high-end 32-bit rk3288 SoC.

  Notable updates to existing platforms are usually for added on-chip
  peripherals, including:

   - ASpeed AST2xxx (various)

   - Allwinner (cpufreq, thermal, Pinephone touchscreen)

   - Amlogic Meson (audio, gpu dvdfs, board updates)

   - Arm Versatile

   - Broadcom (board updates for switch ports, Raspberry pi clock updates)

   - Hisilicon (various)

   - Intel/Altera SoCFPGA (various)

   - Marvell Armada 7xxx/8xxx (smmu)

   - Marvell MMP (GPU on mmp2/mmp3)

   - Mediatek mt8183 (USB, pericfg)

   - NXP Layerscape (VPU, thermal, DSPI)

   - NXP i.MX (VPU, bindings, board updates)

   - Nvidia Tegra194 (GPU)

   - Qualcomm (GPU, Interconnect, ...)

   - Renesas R-Car (SPI, IPMMU, board updates)

   - STMicroelectronics STM32 (various)

   - Samsung Exynos (various)

   - Socionext Uniphier (updates to serial, and pcie)

   - TI K3 (serdes, usb3, audio, sd, chipid)

   - TI OMAP (IPU/DSP remoteproc changes, dropping platform data)"

* tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (605 commits)
  arm64: dts: meson: odroid-n2: add jack audio output support
  arm64: dts: meson: odroid-n2: enable audio loopback
  ARM: dts: berlin: Align L2 cache-controller nodename with dtschema
  arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device tree
  arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree
  arm64: dts: qcom: msm8992: Add RPMCC node
  arm64: dts: qcom: msm8992: Add PSCI support.
  arm64: dts: qcom: msm8992: Add PMU node
  arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes
  arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter device
  arm64: dts: qcom: msm8992: Add a SCM node
  arm64: dts: qcom: msm8992: Add a proper CPU map
  arm64: dts: qcom: bullhead: Move UART pinctrl to SoC
  arm64: dts: qcom: bullhead: Add qcom,msm-id
  arm64: dts: qcom: msm8992: Fix SDHCI1
  arm64: dts: qcom: msm8992: Modernize the DTS style
  arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW)
  arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead.
  arm64: dts: qcom: msm8994: Add support for SMD RPM
  arm64: dts: qcom: msm8992: Add a label to rpm-requests
  ...

1 files changed, 189 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 5303821300b4..96a5ec89b5f0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -82,6 +82,91 @@
 		ranges = <0 0 0 0xffffffff>;
 		compatible = "simple-bus";
 
+		ssphy_1: phy@58000 {
+			compatible = "qcom,ipq8074-qmp-usb3-phy";
+			reg = <0x00058000 0x1c4>;
+			#clock-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_USB1_AUX_CLK>,
+				<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+				<&xo>;
+			clock-names = "aux", "cfg_ahb", "ref";
+
+			resets =  <&gcc GCC_USB1_PHY_BCR>,
+				<&gcc GCC_USB3PHY_1_PHY_BCR>;
+			reset-names = "phy","common";
+			status = "disabled";
+
+			usb1_ssphy: lane@58200 {
+				reg = <0x00058200 0x130>,       /* Tx */
+				      <0x00058400 0x200>,     /* Rx */
+				      <0x00058800 0x1f8>,     /* PCS  */
+				      <0x00058600 0x044>;     /* PCS misc*/
+				#phy-cells = <0>;
+				clocks = <&gcc GCC_USB1_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "gcc_usb1_pipe_clk_src";
+			};
+		};
+
+		qusb_phy_1: phy@59000 {
+			compatible = "qcom,ipq8074-qusb2-phy";
+			reg = <0x00059000 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+				 <&xo>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+			status = "disabled";
+		};
+
+		ssphy_0: phy@78000 {
+			compatible = "qcom,ipq8074-qmp-usb3-phy";
+			reg = <0x00078000 0x1c4>;
+			#clock-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_USB0_AUX_CLK>,
+				<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				<&xo>;
+			clock-names = "aux", "cfg_ahb", "ref";
+
+			resets =  <&gcc GCC_USB0_PHY_BCR>,
+				<&gcc GCC_USB3PHY_0_PHY_BCR>;
+			reset-names = "phy","common";
+			status = "disabled";
+
+			usb0_ssphy: lane@78200 {
+				reg = <0x00078200 0x130>,       /* Tx */
+				      <0x00078400 0x200>,     /* Rx */
+				      <0x00078800 0x1f8>,     /* PCS  */
+				      <0x00078600 0x044>;     /* PCS misc*/
+				#phy-cells = <0>;
+				clocks = <&gcc GCC_USB0_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "gcc_usb0_pipe_clk_src";
+			};
+		};
+
+		qusb_phy_0: phy@79000 {
+			compatible = "qcom,ipq8074-qusb2-phy";
+			reg = <0x00079000 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&xo>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+		};
+
 		pcie_phy0: phy@86000 {
 			compatible = "qcom,ipq8074-qmp-pcie-phy";
 			reg = <0x00086000 0x1000>;
@@ -169,6 +254,28 @@
 			#reset-cells = <0x1>;
 		};
 
+		sdhc_1: sdhci@7824900 {
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x7824900 0x500>, <0x7824000 0x800>;
+			reg-names = "hc_mem", "core_mem";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&xo>,
+				 <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>;
+			clock-names = "xo", "iface", "core";
+			max-frequency = <384000000>;
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			bus-width = <8>;
+
+			status = "disabled";
+		};
+
 		blsp_dma: dma@7884000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x07884000 0x2b000>;
@@ -294,6 +401,88 @@
 			status = "disabled";
 		};
 
+		usb_0: usb@8af8800 {
+			compatible = "qcom,dwc3";
+			reg = <0x08af8800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+				<&gcc GCC_USB0_MASTER_CLK>,
+				<&gcc GCC_USB0_SLEEP_CLK>,
+				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			clock-names = "sys_noc_axi",
+				"master",
+				"sleep",
+				"mock_utmi";
+
+			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+					  <&gcc GCC_USB0_MASTER_CLK>,
+					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <133330000>,
+						<133330000>,
+						<19200000>;
+
+			resets = <&gcc GCC_USB0_BCR>;
+			status = "disabled";
+
+			dwc_0: dwc3@8a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x8a00000 0xcd00>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&qusb_phy_0>, <&usb0_ssphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				snps,is-utmi-l1-suspend;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				dr_mode = "host";
+			};
+		};
+
+		usb_1: usb@8cf8800 {
+			compatible = "qcom,dwc3";
+			reg = <0x08cf8800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
+				<&gcc GCC_USB1_MASTER_CLK>,
+				<&gcc GCC_USB1_SLEEP_CLK>,
+				<&gcc GCC_USB1_MOCK_UTMI_CLK>;
+			clock-names = "sys_noc_axi",
+				"master",
+				"sleep",
+				"mock_utmi";
+
+			assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
+					  <&gcc GCC_USB1_MASTER_CLK>,
+					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <133330000>,
+						<133330000>,
+						<19200000>;
+
+			resets = <&gcc GCC_USB1_BCR>;
+			status = "disabled";
+
+			dwc_1: dwc3@8c00000 {
+				compatible = "snps,dwc3";
+				reg = <0x8c00000 0xcd00>;
+				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&qusb_phy_1>, <&usb1_ssphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				snps,is-utmi-l1-suspend;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				dr_mode = "host";
+			};
+		};
+
 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
 			interrupt-controller;