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authorChandrakala Chavva <cchavva@caviumnetworks.com>2011-02-18 00:57:52 +0300
committerRalf Baechle <ralf@linux-mips.org>2011-05-19 12:55:49 +0400
commit7716e6548abed1582a7759666e79d5c612a906c7 (patch)
treeebd12144faf525408ed82f6415804b02ee712440 /arch/mips/include/asm/mach-cavium-octeon
parentb32ee693eb106172f89639acff88dc8fee8ba3e2 (diff)
downloadlinux-7716e6548abed1582a7759666e79d5c612a906c7.tar.xz
Octeon: Fix interrupt irq settings for performance counters.
Octeon uses different interrupt irq for timer and performance counters. Set CvmCtl[IPPCI] to correct irq value very early. Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/2085/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon')
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 0b2b5eb22e9b..dedef7d2b01f 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,11 @@
# CN30XX Disable instruction prefetching
or v0, v0, 0x2000
skip:
+ # First clear off CvmCtl[IPPCI] bit and move the performance
+ # counters interrupt to IRQ 6
+ li v1, ~(7 << 7)
+ and v0, v0, v1
+ ori v0, v0, (6 << 7)
# Write the cavium control register
dmtc0 v0, CP0_CVMCTL_REG
sync