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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2023-02-27 21:46:13 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-02-28 01:44:57 +0300 |
| commit | fea8826d5fdc4ff5c93e883a738597129614039c (patch) | |
| tree | a4427ea43c2031f51e2d7a14ad912bfb3399f55a /arch/mips/kernel/smp-cps.c | |
| parent | dd8314739a1ff8ed081d3a06f5f87045f7384636 (diff) | |
| download | linux-fea8826d5fdc4ff5c93e883a738597129614039c.tar.xz | |
MIPS: smp-cps: Don't rely on CP0_CMGCRBASE
CP0_CMGCRBASE is not always available on CPS enabled system
such as early proAptiv.
For early SMP bring up where we can't safely access memeory,
we patch the entry of CPS NMI vector to inject CMGCR address
directly into register during early core bringup.
For VPE bringup as the core is already coherenct at that point
we just read the variable to obtain the address.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/kernel/smp-cps.c')
| -rw-r--r-- | arch/mips/kernel/smp-cps.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index f2df0cae1b4d..4fc288bb85b9 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -162,6 +162,8 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) */ entry_code = (u32 *)&mips_cps_core_entry; uasm_i_addiu(&entry_code, 16, 0, cca); + UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); + BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); blast_dcache_range((unsigned long)&mips_cps_core_entry, (unsigned long)entry_code); bc_wback_inv((unsigned long)&mips_cps_core_entry, |