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authorNicholas Piggin <npiggin@gmail.com>2022-09-26 06:40:54 +0300
committerMichael Ellerman <mpe@ellerman.id.au>2022-09-28 12:22:12 +0300
commitdab3b8f4fd09c22e8dbb2d9608194c7d52252f33 (patch)
treed4466f017436a103218cf6c93243968d56568a81 /arch/powerpc/lib/copypage_64.S
parent17773afdcd1589c5925a984f512330410cb2ba4f (diff)
downloadlinux-dab3b8f4fd09c22e8dbb2d9608194c7d52252f33.tar.xz
powerpc/64: asm use consistent global variable declaration and access
Use helper macros to access global variables, and place them in .data sections rather than in .toc. Putting addresses in TOC is not required because the kernel is linked with a single TOC. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220926034057.2360083-3-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc/lib/copypage_64.S')
-rw-r--r--arch/powerpc/lib/copypage_64.S7
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/powerpc/lib/copypage_64.S b/arch/powerpc/lib/copypage_64.S
index d1091b5ee5da..6812cb19d04a 100644
--- a/arch/powerpc/lib/copypage_64.S
+++ b/arch/powerpc/lib/copypage_64.S
@@ -9,11 +9,6 @@
#include <asm/export.h>
#include <asm/feature-fixups.h>
- .section ".toc","aw"
-PPC64_CACHES:
- .tc ppc64_caches[TC],ppc64_caches
- .section ".text"
-
_GLOBAL_TOC(copy_page)
BEGIN_FTR_SECTION
lis r5,PAGE_SIZE@h
@@ -24,7 +19,7 @@ FTR_SECTION_ELSE
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
ori r5,r5,PAGE_SIZE@l
BEGIN_FTR_SECTION
- ld r10,PPC64_CACHES@toc(r2)
+ LOAD_REG_ADDR(r10, ppc64_caches)
lwz r11,DCACHEL1LOGBLOCKSIZE(r10) /* log2 of cache block size */
lwz r12,DCACHEL1BLOCKSIZE(r10) /* get cache block size */
li r9,0