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| author | Nicholas Piggin <npiggin@gmail.com> | 2022-09-26 06:40:57 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2022-09-28 12:22:12 +0300 |
| commit | 3569d84bb26f6f07d426446da3d2c836180f1565 (patch) | |
| tree | 677340fd4c7ed38f3dd3c1964aa8b270fe768192 /arch/powerpc/mm/nohash | |
| parent | 8e93fb33c84f68db20c0bc2821334a4c54c3e251 (diff) | |
| download | linux-3569d84bb26f6f07d426446da3d2c836180f1565.tar.xz | |
powerpc/64e: provide an addressing macro for use with TOC in alternate register
The interrupt entry code carefully saves a minimal number of registers,
so in some places the TOC is required, it is loaded into a different
register, so provide a macro that can supply an alternate TOC register.
This continues to use got addressing because TOC-relative results in
"got/toc optimization is not supported" messages by the linker. Having
r2 be one of the saved registers and using that for TOC addressing may
be the best way to avoid that and switch this to TOC addressing.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220926034057.2360083-6-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc/mm/nohash')
| -rw-r--r-- | arch/powerpc/mm/nohash/tlb_low_64e.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/mm/nohash/tlb_low_64e.S b/arch/powerpc/mm/nohash/tlb_low_64e.S index b3b3dfeec8f5..76cf456d7976 100644 --- a/arch/powerpc/mm/nohash/tlb_low_64e.S +++ b/arch/powerpc/mm/nohash/tlb_low_64e.S @@ -1119,7 +1119,7 @@ tlb_load_linear: * final implementation, especially when dealing with hypervisors */ __LOAD_PACA_TOC(r11) - ld r11,linear_map_top@got(r11) + LOAD_REG_ADDR_ALTTOC(r11, r11, linear_map_top) ld r10,0(r11) tovirt(10,10) cmpld cr0,r16,r10 |