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authorAlistair Popple <alistair@popple.id.au>2017-09-06 04:49:00 +0300
committerMichael Ellerman <mpe@ellerman.id.au>2017-11-13 00:00:30 +0300
commit1b2c2b12386f9bb009a2249eca00e01a9d76d7c1 (patch)
treee521dd43b3565c4f3157f277a9b4647393b37ea4 /arch/powerpc/platforms/powernv/pci.h
parent2a31ad093bb1b8c1f1e04cbe222ad17bc09c4534 (diff)
downloadlinux-1b2c2b12386f9bb009a2249eca00e01a9d76d7c1.tar.xz
powerpc/powernv/npu: Don't explicitly flush nmmu tlb
The nest mmu required an explicit flush as a tlbi would not flush it in the same way as the core. However an alternate firmware fix exists which should eliminate the need for this flush, so instead add a device-tree property (ibm,nmmu-flush) on the NVLink2 PHB to enable it only if required. Signed-off-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/platforms/powernv/pci.h')
-rw-r--r--arch/powerpc/platforms/powernv/pci.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 56d1f272d4ad..96151b3a2dd4 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -187,6 +187,9 @@ struct pnv_phb {
/* Bitmask for MMIO register usage */
unsigned long mmio_atsd_usage;
+
+ /* Do we need to explicitly flush the nest mmu? */
+ bool nmmu_flush;
} npu;
#ifdef CONFIG_CXL_BASE