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| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2023-09-13 19:39:03 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-10-12 16:14:09 +0300 |
| commit | db3c01c7a3081c6a6a50570e48bdbea509ba30e4 (patch) | |
| tree | 17fa10411b15b4119920eef06a5e717470b52412 /arch/riscv/include/asm/csr.h | |
| parent | d21b5d342fc12eb0a0f812864aa58aa9bb2c0599 (diff) | |
| download | linux-db3c01c7a3081c6a6a50570e48bdbea509ba30e4.tar.xz | |
RISCV: KVM: Add senvcfg context save/restore
Add senvcfg context save/restore for guest VCPUs and also add it to the
ONE_REG interface to allow its access from user space.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include/asm/csr.h')
| -rw-r--r-- | arch/riscv/include/asm/csr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 5717004d80fb..65b871dbf7e8 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -287,6 +287,7 @@ #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +#define CSR_SENVCFG 0x10a #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 |