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| author | Andy Chiu <andy.chiu@sifive.com> | 2023-06-27 04:55:55 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-07-01 17:38:22 +0300 |
| commit | 5c93c4c72fbc69f0f1cdf43c9402b923314e67c8 (patch) | |
| tree | dba54ed4062320b45b8c700593cc09325ee9aa32 /arch/riscv | |
| parent | 75b59f2a90aa7ccac62e3dcb680dfb967b341431 (diff) | |
| download | linux-5c93c4c72fbc69f0f1cdf43c9402b923314e67c8.tar.xz | |
selftests: Test RISC-V Vector's first-use handler
This add a test to check if the kernel zero-initializes all V registers
after the first-use trap handler returns.
If V registers are not zero-initialized, then the test should fail one
out of several runs:
```
root@sifive-fpga:~# ./v_initval_nolibc
# vl = 256
not ok 1 detect stale values on v-regesters
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 4c 41 4e 47 3d 43 0 50 41 54 48 3d 2f 75 73
72 2f 6c 6f 63 61 6c 2f 73 62 69 6e 3a 2f 75 73
72 2f 6c 6f 63 61 6c 2f 62 69 6e 3a 2f 75 73 72
ff ff 81 0 0 0 0 0 0 0 0 0 0 0 0 0
```
Otherwise, the test passes without errors each run.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20230627015556.12329-3-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv')
0 files changed, 0 insertions, 0 deletions