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authorLin Ming <ming.m.lin@intel.com>2010-03-18 13:33:12 +0300
committerIngo Molnar <mingo@elte.hu>2010-03-18 19:04:02 +0300
commitcb7d6b5053e86598735d9af19930f5929f007b7f (patch)
treeb707d913470443c05bd637d4b7fbab3926e0ba1c /arch/x86/include/asm/perf_event_p4.h
parentf34edbc1cdb0f8f83d94e1d668dd6e41abf0defb (diff)
downloadlinux-cb7d6b5053e86598735d9af19930f5929f007b7f.tar.xz
perf, x86: Add cache events for the Pentium-4 PMU
Move the HT bit setting code from p4_pmu_event_map to p4_hw_config. So the cache events can get HT bit set correctly. Tested on my P4 desktop, below 6 cache events work: L1-dcache-load-misses LLC-load-misses dTLB-load-misses dTLB-store-misses iTLB-loads iTLB-load-misses Signed-off-by: Lin Ming <ming.m.lin@intel.com> Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Peter Zijlstra <peterz@infradead.org> LKML-Reference: <1268908392.13901.128.camel@minggr.sh.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/perf_event_p4.h')
-rw-r--r--arch/x86/include/asm/perf_event_p4.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 7d3406a2773c..871249cf4d2b 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -708,4 +708,14 @@ enum P4_EVENTS_ATTR {
P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, BOGUS, 1),
};
+enum {
+ KEY_P4_L1D_OP_READ_RESULT_MISS,
+ KEY_P4_LL_OP_READ_RESULT_MISS,
+ KEY_P4_DTLB_OP_READ_RESULT_MISS,
+ KEY_P4_DTLB_OP_WRITE_RESULT_MISS,
+ KEY_P4_ITLB_OP_READ_RESULT_ACCESS,
+ KEY_P4_ITLB_OP_READ_RESULT_MISS,
+ KEY_P4_UOP_TYPE,
+};
+
#endif /* PERF_EVENT_P4_H */