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| author | Tony Luck <tony.luck@intel.com> | 2022-02-01 02:01:08 +0300 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-02-01 18:15:19 +0300 |
| commit | 00a2f23eef7d1fa6c2dfdc613857b84fbf5e2b3b (patch) | |
| tree | ab88738de6a22311e9bf260341b856e2845009bf /arch/x86/kernel/cpu/scattered.c | |
| parent | 0dcab41d3487acadf64d0667398e032341bd9918 (diff) | |
| download | linux-00a2f23eef7d1fa6c2dfdc613857b84fbf5e2b3b.tar.xz | |
x86/cpu: X86_FEATURE_INTEL_PPIN finally has a CPUID bit
After nine generations of adding to model specific list of CPUs that
support PPIN (Protected Processor Inventory Number) Intel allocated
a CPUID bit to enumerate the MSRs.
CPUID(EAX=7, ECX=1).EBX bit 0 enumerates presence of MSR_PPIN_CTL and
MSR_PPIN. Add it to the "scattered" CPUID bits and add an entry to the
ppin_cpuids[] x86_match_cpu() array to catch Intel CPUs that implement
it.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220131230111.2004669-3-tony.luck@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/scattered.c')
| -rw-r--r-- | arch/x86/kernel/cpu/scattered.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 21d1f062895a..4143b1e4c5c6 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -26,6 +26,7 @@ struct cpuid_bit { static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, + { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 }, { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, |