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authorLike Xu <likexu@tencent.com>2023-06-03 04:10:55 +0300
committerSean Christopherson <seanjc@google.com>2023-06-07 03:31:44 +0300
commit1c2bf8a6b045a6ac4e75a7a07fde70db63e5a380 (patch)
tree8bf7f1b2e759dd2f19e65aa636cb0f11a71aa8de /arch/x86/kvm/svm/pmu.c
parentd338d8789e64b2d8ed2f82f9364c415d6efa118d (diff)
downloadlinux-1c2bf8a6b045a6ac4e75a7a07fde70db63e5a380.tar.xz
KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap
Cap the number of general purpose counters enumerated on AMD to what KVM actually supports, i.e. don't allow userspace to coerce KVM into thinking there are more counters than actually exist, e.g. by enumerating X86_FEATURE_PERFCTR_CORE in guest CPUID when its not supported. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Like Xu <likexu@tencent.com> [sean: massage changelog] Link: https://lore.kernel.org/r/20230603011058.1038821-10-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'arch/x86/kvm/svm/pmu.c')
-rw-r--r--arch/x86/kvm/svm/pmu.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
index e5c69062a909..c03958063a76 100644
--- a/arch/x86/kvm/svm/pmu.c
+++ b/arch/x86/kvm/svm/pmu.c
@@ -170,6 +170,9 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
else
pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS;
+ pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters,
+ kvm_pmu_cap.num_counters_gp);
+
pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
pmu->reserved_bits = 0xfffffff000280000ull;
pmu->raw_event_mask = AMD64_RAW_EVENT_MASK;