diff options
author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-05-23 12:33:41 +0300 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2022-06-16 03:24:13 +0300 |
commit | a0bc8ae5a0d7c79e376f400d989698194c6af7a1 (patch) | |
tree | b057d758695933af48021a77ca075f81230a92e5 /drivers/clk/mediatek/clk-mt8183.c | |
parent | fb91526b5fb04133799bc708661b467226caa032 (diff) | |
download | linux-a0bc8ae5a0d7c79e376f400d989698194c6af7a1.tar.xz |
clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
The infra_ao reset is needed for MT8192 and MT8195.
- Add mtk_clk_rst_desc for MT8192 and MT8195
- Add register reset controller function for MT8192 infra_ao.
- Move definition of infra reset from cl-mt8183.c to reset.h
because it's the same definition with MT8192 and MT8195.
- Add new definition of infra reset_4 for MT8192 and MT8195.
- Add infra_ao_idx_map for MT8192 and MT8195.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[Nícolas: Test for MT8192]
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-15-rex-bc.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8183.c')
-rw-r--r-- | drivers/clk/mediatek/clk-mt8183.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index b1d810f85b71..8512101e1189 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -18,12 +18,6 @@ #include <dt-bindings/clock/mt8183-clk.h> -/* Infra global controller reset set register */ -#define INFRA_RST0_SET_OFFSET 0x120 -#define INFRA_RST1_SET_OFFSET 0x130 -#define INFRA_RST2_SET_OFFSET 0x140 -#define INFRA_RST3_SET_OFFSET 0x150 - static DEFINE_SPINLOCK(mt8183_clk_lock); static const struct mtk_fixed_clk top_fixed_clks[] = { |