diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-21 18:35:56 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-02-22 11:51:20 +0300 |
| commit | 73421f2a48e6bd1d1024a09aedbc9c662cb88e77 (patch) | |
| tree | af3c26b941e6920fbb80fb6fde839ed5353b50b2 /drivers/clk/renesas/r8a779f0-cpg-mssr.c | |
| parent | 5447d32c55592610969fa7e825a591c4104f0134 (diff) | |
| download | linux-73421f2a48e6bd1d1024a09aedbc9c662cb88e77.tar.xz | |
clk: renesas: r8a779f0: Add PFC clock
Add the module clock used by the Pin Function (PFC/GPIO) controller
on the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/4ef3d3dfe714ad75112e4886efea0b66e40a33bc.1645457502.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas/r8a779f0-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 123c1b01550d..76b441965037 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("wdt", 907, R8A779F0_CLK_R), + DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), }; static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { |