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| author | Bill Huang <bilhuang@nvidia.com> | 2015-06-19 00:28:35 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-12-17 15:37:55 +0300 |
| commit | 139fd30943c3c8ed76d0ce08ff711cfff3b118ec (patch) | |
| tree | e5d3d9bec2145062c1ad25c44f50d21ab95737bb /drivers/clk/tegra/clk-id.h | |
| parent | 0ef9db6cf24dbb58118818e64198d9a030e4697e (diff) | |
| download | linux-139fd30943c3c8ed76d0ce08ff711cfff3b118ec.tar.xz | |
clk: tegra: Add Super Gen5 Logic
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-id.h')
0 files changed, 0 insertions, 0 deletions