diff options
| author | Frank Li <Frank.Li@nxp.com> | 2023-08-21 19:16:09 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-08-22 17:41:02 +0300 |
| commit | c26e611433aaa064691343c0168f4671eb5cfa42 (patch) | |
| tree | f81840e193f2fa8a4de2797b942906a93b5247bf /drivers/dma/fsl-edma-main.c | |
| parent | 9e006b243962a42f6927d2d9fe1a7b0a29f45265 (diff) | |
| download | linux-c26e611433aaa064691343c0168f4671eb5cfa42.tar.xz | |
dmaengine: fsl-edma: Remove enum edma_version
The enum edma_version, which defines v1, v2, and v3, is a software concept
used to distinguish IP differences. However, it is not aligned with the
chip reference manual. According to the 7ulp reference manual, it should
be edma2. In the future, there will be edma3, edma4, and edma5, which
could cause confusion. To avoid this confusion, remove the edma_version
and instead use drvdata->flags to distinguish the IP difference.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230821161617.2142561-5-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/fsl-edma-main.c')
| -rw-r--r-- | drivers/dma/fsl-edma-main.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index a318ad6e40c2..389e5f9875dc 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -236,22 +236,20 @@ static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) } static struct fsl_edma_drvdata vf610_data = { - .version = v1, .dmamuxs = DMAMUX_NR, + .flags = FSL_EDMA_DRV_WRAP_IO, .setup_irq = fsl_edma_irq_init, }; static struct fsl_edma_drvdata ls1028a_data = { - .version = v1, .dmamuxs = DMAMUX_NR, - .flags = FSL_EDMA_DRV_MUX_SWAP, + .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, .setup_irq = fsl_edma_irq_init, }; static struct fsl_edma_drvdata imx7ulp_data = { - .version = v3, .dmamuxs = 1, - .flags = FSL_EDMA_DRV_HAS_DMACLK, + .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, .setup_irq = fsl_edma2_irq_init, }; |