diff options
author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2021-05-20 15:17:15 +0300 |
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committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2021-05-20 15:20:52 +0300 |
commit | 2b71b66ac0415db5e4b9e67b11e3af7b485bb421 (patch) | |
tree | 2072bea53678ad4e0a2d1651de0698a01a09ab25 /drivers/gpio/gpio-wcove.c | |
parent | 5d9936648285b8ccb6b61257dd2ddd76f9cd719a (diff) | |
download | linux-2b71b66ac0415db5e4b9e67b11e3af7b485bb421.tar.xz |
gpio: wcove: Split error handling for CTRL and IRQ registers
The wcove_gpio_dbg_show() uses one message to all possible error reads.
Split it to two for CTRL and IRQ registers.
While at it, switch to use dev_err() instead of pr_err().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'drivers/gpio/gpio-wcove.c')
-rw-r--r-- | drivers/gpio/gpio-wcove.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c index 5ce315f64dc5..16a0fae1e32e 100644 --- a/drivers/gpio/gpio-wcove.c +++ b/drivers/gpio/gpio-wcove.c @@ -364,8 +364,7 @@ static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) return IRQ_HANDLED; } -static void wcove_gpio_dbg_show(struct seq_file *s, - struct gpio_chip *chip) +static void wcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { unsigned int ctlo, ctli, irq_mask, irq_status; struct wcove_gpio *wg = gpiochip_get_data(chip); @@ -374,10 +373,15 @@ static void wcove_gpio_dbg_show(struct seq_file *s, for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) { ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); + if (ret) { + dev_err(wg->dev, "Failed to read registers: CTRL out/in\n"); + break; + } + ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask); ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status); if (ret) { - pr_err("Failed to read registers: ctrl out/in or irq status/mask\n"); + dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n"); break; } |