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author | Felix Kuehling <felix.kuehling@amd.com> | 2024-01-25 22:12:43 +0300 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2024-02-16 23:41:50 +0300 |
commit | 34a1de0f79352086884553f78db271f957a98583 (patch) | |
tree | fc2b16a53d8a65b0417d7e6fd1c7b423a6071548 /drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c | |
parent | 79863ddee8eb5969c1bcaf0d41dd886ba6166c2e (diff) | |
download | linux-34a1de0f79352086884553f78db271f957a98583.tar.xz |
drm/amdkfd: Relocate TBA/TMA to opposite side of VM hole
The TBA and TMA, along with an unused IB allocation, reside at low
addresses in the VM address space. A stray VM fault which hits these
pages must be serviced by making their page table entries invalid.
The scheduler depends upon these pages being resident and fails,
preventing a debugger from inspecting the failure state.
By relocating these pages above 47 bits in the VM address space they
can only be reached when bits [63:48] are set to 1. This makes it much
less likely for a misbehaving program to generate accesses to them.
The current placement at VA (PAGE_SIZE*2) is readily hit by a NULL
access with a small offset.
v2:
- Move it to the reserved space to avoid concflicts with Mesa
- Add macros to make reserved space management easier
v3:
- Move VM max PFN calculation into AMDGPU_VA_RESERVED macros
Cc: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c')
0 files changed, 0 insertions, 0 deletions