diff options
| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2019-07-12 22:06:06 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 18:53:36 +0300 |
| commit | 9adc8050bf3ca3e49c65e13259a4c310640542f1 (patch) | |
| tree | e17c0d9813669bfd8ce47002f793b8f8a9e7d34f /drivers/gpu/drm/amd/display/dc/clk_mgr | |
| parent | 0b226322434c7786381d7a594efca9cc46f85211 (diff) | |
| download | linux-9adc8050bf3ca3e49c65e13259a4c310640542f1.tar.xz | |
drm/amd/display: make firmware info only load once during dc_bios create
Currently every time DC wants to access firmware info we make a call
into VBIOS. This makes no sense as there is nothing that can change
runtime inside fw info and can cause issues when calling unstable
bios during bringup.
This change eliminate this behavior by only calling bios once for fw
info and keeping it stored as part of dc_bios.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 17 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 6 |
2 files changed, 8 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 814450fefffa..c5c8c4901eed 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -273,18 +273,12 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce) { struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; - struct integrated_info info = { { { 0 } } }; - struct dc_firmware_info fw_info = { { 0 } }; int i; if (bp->integrated_info) - info = *bp->integrated_info; - - clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq; + clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; if (clk_mgr_dce->dentist_vco_freq_khz == 0) { - bp->funcs->get_firmware_info(bp, &fw_info); - clk_mgr_dce->dentist_vco_freq_khz = - fw_info.smu_gpu_pll_output_freq; + clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq; if (clk_mgr_dce->dentist_vco_freq_khz == 0) clk_mgr_dce->dentist_vco_freq_khz = 3600000; } @@ -317,9 +311,10 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce) /*Do not allow bad VBIOS/SBIOS to override with invalid values, * check for > 100MHz*/ - if (info.disp_clk_voltage[i].max_supported_clk >= 100000) - clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = - info.disp_clk_voltage[i].max_supported_clk; + if (bp->integrated_info) + if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000) + clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = + bp->integrated_info->disp_clk_voltage[i].max_supported_clk; } if (!debug->disable_dfs_bypass && bp->integrated_info) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c index caf8a4a4e442..39c1dea9942b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c @@ -246,7 +246,6 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_ { struct dc_debug_options *debug = &ctx->dc->debug; struct dc_bios *bp = ctx->dc_bios; - struct dc_firmware_info fw_info = { { 0 } }; clk_mgr->base.ctx = ctx; clk_mgr->pp_smu = pp_smu; @@ -262,9 +261,8 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_ if (bp->integrated_info) clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; - if (clk_mgr->dentist_vco_freq_khz == 0) { - bp->funcs->get_firmware_info(bp, &fw_info); - clk_mgr->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq; + if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) { + clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq; if (clk_mgr->dentist_vco_freq_khz == 0) clk_mgr->dentist_vco_freq_khz = 3600000; } |