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author | Wesley Chalmers <Wesley.Chalmers@amd.com> | 2021-05-07 00:16:00 +0300 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-08 19:22:42 +0300 |
commit | 39a1355feff934d967240f2212f5a25f9f6b1357 (patch) | |
tree | 80ff9fa63615fb353ea56ebb440df9359468051e /drivers/gpu/drm/amd/display/dc/dcn301 | |
parent | b4d56e0c508b2ad847aeff5691f67bd2a40034ec (diff) | |
download | linux-39a1355feff934d967240f2212f5a25f9f6b1357.tar.xz |
drm/amd/display: Add interface for ADD & DROP PIXEL Registers
[WHY]
HW has handed down a new sequence that requires access to these
registers.
v2: squash in DCN3.1 fixes (Alex)
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn301')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c index 6e6af02b38f9..97e9be87afd9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c @@ -46,6 +46,8 @@ static const struct dccg_funcs dccg301_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .otg_add_pixel = dccg2_otg_add_pixel, + .otg_drop_pixel = dccg2_otg_drop_pixel, .dccg_init = dccg2_init }; |