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authorOvidiu Bunea <ovidiu.bunea@amd.com>2023-09-07 01:03:19 +0300
committerAlex Deucher <alexander.deucher@amd.com>2023-09-26 23:54:18 +0300
commit3d457727dad87ba2d409334d488141e5578a821d (patch)
tree3585e7f6bb8e26b05db603cb75b421ef34b632e9 /drivers/gpu/drm/amd/display/dc/dcn30
parent5710c6c0bda39789ada08fbe7b64aa13654b2dd2 (diff)
downloadlinux-3d457727dad87ba2d409334d488141e5578a821d.tar.xz
drm/amd/display: Use optc32 instead of optc30 in DC
Change DC to use optc32, which uses REG_UPDATE instead of REG_SET. REG_SET clears OTG_H_TIMING_DIV_MODE_MANUAL which must be set to 1 in some specific HDMI configurations. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn30')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index 5bf4d0aa6230..b97bdb868a0e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -207,7 +207,7 @@ void optc3_set_odm_bypass(struct timing_generator *optc,
);
h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
- REG_SET(OTG_H_TIMING_CNTL, 0,
+ REG_UPDATE(OTG_H_TIMING_CNTL,
OTG_H_TIMING_DIV_MODE, h_div);
REG_SET(OPTC_MEMORY_CONFIG, 0,