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| author | Wenjing Liu <wenjing.liu@amd.com> | 2024-03-15 19:03:12 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-04-10 04:51:32 +0300 |
| commit | 62297b71a02d73e761470f7907ec1ce63bb3615c (patch) | |
| tree | e71737ca94a021c660350e9e53792a37db60e23c /drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h | |
| parent | 7ae0caf348830d92661296ec46ec5b4cfeb440b2 (diff) | |
| download | linux-62297b71a02d73e761470f7907ec1ce63bb3615c.tar.xz | |
drm/amd/display: optimize dml2 pipe resource allocation order
[why]
There could be cases that we are transition from MPC to ODM combine.
In this case if we map pipes before unmapping MPC pipes, we might
temporarly run out of pipes. The change reorders pipe resource
allocation. So we unmapping pipes before mapping new pipes.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h')
0 files changed, 0 insertions, 0 deletions