diff options
author | Dave Airlie <airlied@redhat.com> | 2024-02-13 04:32:23 +0300 |
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committer | Dave Airlie <airlied@redhat.com> | 2024-02-13 04:32:23 +0300 |
commit | b344e64fbda303b767a3844ee739a596a9c3679e (patch) | |
tree | caeec9924ea5522f008e42d89a7bf4286e759bc3 /drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h | |
parent | 0de62399883d5077fd13d0926f5128a7e038b40c (diff) | |
parent | d5597444032b2f5c8624918fb5b29be5bba78a3c (diff) | |
download | linux-b344e64fbda303b767a3844ee739a596a9c3679e.tar.xz |
Merge tag 'amd-drm-next-6.9-2024-02-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.9-2024-02-09:
amdgpu:
- Validate DMABuf imports in compute VMs
- Add RAS ACA framework
- PSP 13 fixes
- Misc code cleanups
- Replay fixes
- Atom interpretor PS, WS bounds checking
- DML2 fixes
- Audio fixes
- DCN 3.5 Z state fixes
- Remove deprecated ida_simple usage
- UBSAN fixes
- RAS fixes
- Enable seq64 infrastructure
- DC color block enablement
- Documentation updates
- DC documentation updates
- DMCUB updates
- S3 fixes
- VCN 4.0.5 fixes
- DP MST fixes
- SR-IOV fixes
amdkfd:
- Validate DMABuf imports in compute VMs
- SVM fixes
- Trap handler updates
radeon:
- Atom interpretor PS, WS bounds checking
- Misc code cleanups
UAPI:
- Bump KFD version so UMDs know that the fixes that enable the management of
VA mappings in compute VMs using the GEM_VA ioctl for DMABufs exported from KFD are present
- Add INFO query for input power. This matches the existing INFO query for average
power. Used in gaming HUDs, etc.
Example userspace: https://github.com/Umio-Yasuno/libdrm-amdgpu-sys-rs/tree/input_power
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240209221459.5453-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h index 6137cf09aa54..554cfab5ab24 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h @@ -155,7 +155,6 @@ struct hwseq_private_funcs { void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context); -#ifdef CONFIG_DRM_AMD_DC_FP void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); void (*update_force_pstate)(struct dc *dc, struct dc_state *context); void (*update_mall_sel)(struct dc *dc, struct dc_state *context); @@ -165,8 +164,14 @@ struct hwseq_private_funcs { void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx); void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context); + enum dc_status (*apply_single_controller_ctx_to_hw)( + struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct dc *dc); bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx); -#endif + void (*reset_back_end_for_pipe)(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context); }; struct dce_hwseq { |