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| author | Roman Li <Roman.Li@amd.com> | 2020-09-29 18:21:58 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-05 22:15:56 +0300 |
| commit | 3a83e4e64bb1522ddac67ffc787d1c38291e1a65 (patch) | |
| tree | 907efd005ca3c474afd17acae74f53aec1a8836e /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | |
| parent | ac0dc4c5a0760c9a9437d5864c277d9d2554a6ec (diff) | |
| download | linux-3a83e4e64bb1522ddac67ffc787d1c38291e1a65.tar.xz | |
drm/amd/display: Add dcn3.01 support to DC (v2)
Update dc for vangogh support.
v2: fix compilation without DCN 301 set.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 947d6106f341..35d1b85713b2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -62,6 +62,25 @@ struct dcn3_clk_internal { }; #endif + +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +struct dcn301_clk_internal { + int dummy; + uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk + uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk + uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk + uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider + uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow + + uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass + uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass + uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass +}; + +#endif + /* Will these bw structures be ASIC specific? */ #define MAX_NUM_DPM_LVL 8 @@ -262,6 +281,17 @@ struct clk_mgr_funcs { #endif }; +#ifdef CONFIG_DRM_AMD_DC_DCN3_01 +struct dpm_clocks; +struct wartermarks; + +struct smu_watermark_set { + struct watermarks *wm_set; + union large_integer mc_address; +}; + +#endif + struct clk_mgr { struct dc_context *ctx; struct clk_mgr_funcs *funcs; @@ -275,6 +305,9 @@ struct clk_mgr { struct clk_state_registers_and_bypass boot_snapshot; struct clk_bw_params *bw_params; struct pp_smu_wm_range_sets ranges; +#ifdef CONFIG_DRM_AMD_DC_DCN3_01 + struct smu_watermark_set smu_wm_set; +#endif }; /* forward declarations */ |