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authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>2019-09-13 18:33:27 +0300
committerAlex Deucher <alexander.deucher@amd.com>2019-10-11 03:35:01 +0300
commit976035dd4f68d07b6c075fbed501814bfa6fb986 (patch)
treeabb5b6aada4d17040647331af09984c54a8e6fb9 /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
parenta51894f015aff62472b1ccad287d3db6d669f879 (diff)
downloadlinux-976035dd4f68d07b6c075fbed501814bfa6fb986.tar.xz
drm/amd/display: add renoir specific watermark range and clk helper
Doing this allows us to split it for diffrent asics. This design will be helpful for future Asciis. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index f0f3d42a0b6f..f2e21cb9fbd5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -47,7 +47,7 @@
#ifdef CONFIG_DRM_AMD_DC_DCN2_1
/* Will these bw structures be ASIC specific? */
-#define MAX_NUM_DPM_LVL 4
+#define MAX_NUM_DPM_LVL 8
#define WM_SET_COUNT 4
@@ -149,6 +149,7 @@ struct wm_table {
struct clk_bw_params {
unsigned int vram_type;
unsigned int num_channels;
+ unsigned int dispclk_vco_khz;
struct clk_limit_table clk_table;
struct wm_table wm_table;
};