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| author | Vladimir Stempen <vladimir.stempen@amd.com> | 2020-12-29 23:01:12 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-02-23 02:05:48 +0300 |
| commit | 77a2b7265f20ee827e527eaa6f82b87e88388947 (patch) | |
| tree | ad682d99286a0cc1a5e4210837e9402ab55e7366 /drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | |
| parent | 860b0cf52a239a422b89cd652393e1f1c81e161d (diff) | |
| download | linux-77a2b7265f20ee827e527eaa6f82b87e88388947.tar.xz | |
drm/amd/display: Synchronize displays with different timings
[why]
Vendor based fan noise improvement
[how]
Report timing synchronizable when DP streams time frame
difference is less than 0.05 percent. Adjust DP DTOs and
sync displays using MASTER_UPDATE_LOCK_DB_X_Y
Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 754832d216fd..9ff68b67780c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -109,6 +109,12 @@ enum h_timing_div_mode { H_TIMING_DIV_BY4, }; +enum timing_synchronization_type { + NOT_SYNCHRONIZABLE, + TIMING_SYNCHRONIZABLE, + VBLANK_SYNCHRONIZABLE +}; + struct crc_params { /* Regions used to calculate CRC*/ uint16_t windowa_x_start; @@ -292,6 +298,12 @@ struct timing_generator_funcs { uint32_t window_start, uint32_t window_end); void (*set_vtotal_change_limit)(struct timing_generator *optc, uint32_t limit); + void (*align_vblanks)(struct timing_generator *master_optc, + struct timing_generator *slave_optc, + uint32_t master_pixel_clock_100Hz, + uint32_t slave_pixel_clock_100Hz, + uint8_t master_clock_divider, + uint8_t slave_clock_divider); }; #endif |