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authorRodrigo Siqueira <Rodrigo.Siqueira@amd.com>2024-04-10 00:25:23 +0300
committerAlex Deucher <alexander.deucher@amd.com>2024-04-27 00:22:42 +0300
commit5e66f6eaa290093c4542ed216c298000713f92e5 (patch)
treefe105d787a9c8682fbaa5af40675f58edfbaf685 /drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
parente02387408117c5bccbcb123c50519b8a05444ac5 (diff)
downloadlinux-5e66f6eaa290093c4542ed216c298000713f92e5.tar.xz
drm/amd/display: Add some missing HDMI registers for DCN3x
This commit add some missing HDMI control registers to DCN3x. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
index b5bfaa64a9db..fc72c2267060 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
@@ -311,6 +311,10 @@
#define mmPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2
#define mmPHYFSYMCLK_CLOCK_CNTL 0x0057
#define mmPHYFSYMCLK_CLOCK_CNTL_BASE_IDX 2
+#define regHDMICHARCLK0_CLOCK_CNTL 0x004a
+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2
+#define mmHDMICHARCLK0_CLOCK_CNTL 0x004a
+#define mmHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dccg_dccg_dfs_dispdec