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authorMatt Atwood <matthew.s.atwood@intel.com>2022-11-23 21:36:47 +0300
committerMatt Roper <matthew.d.roper@intel.com>2022-11-28 21:18:03 +0300
commit468a4e630c7da8cf586f85cc498d6097aed1ab4b (patch)
tree470902e5d00ea20a5066db498066d461ede58817 /drivers/gpu/drm/i915/gt/intel_gt_regs.h
parentf301a29f143760ce8d3d6b6a8436d45d3448cde6 (diff)
downloadlinux-468a4e630c7da8cf586f85cc498d6097aed1ab4b.tar.xz
drm/i915/dg2: Introduce Wa_18018764978
Wa_18018764978 applies to specific steppings of DG2 (G10 C0+, G11 and G12 A0+). Clean up style in function at the same time. Bspec: 66622 Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221123183648.407058-1-matthew.s.atwood@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gt_regs.h')
-rw-r--r--drivers/gpu/drm/i915/gt/intel_gt_regs.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 3658e12db74b..bdeb31a40623 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -456,6 +456,9 @@
#define GEN8_L3CNTLREG _MMIO(0x7034)
#define GEN8_ERRDETBCTRL (1 << 9)
+#define PSS_MODE2 _MMIO(0x703c)
+#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
+
#define GEN7_SC_INSTDONE _MMIO(0x7100)
#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)