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author | Tina Zhang <tina.zhang@intel.com> | 2018-02-11 09:59:19 +0300 |
---|---|---|
committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-02-14 05:34:44 +0300 |
commit | a26ca6ad4c4aa4afcbfe4c46c33ad98859736245 (patch) | |
tree | 3d766e38edaadda7b83d64ed701a20e4d041a6ca /drivers/gpu/drm/i915/gvt/trace.h | |
parent | 37ad4e68783088ed61493f54194cfccd3c87ab35 (diff) | |
download | linux-a26ca6ad4c4aa4afcbfe4c46c33ad98859736245.tar.xz |
drm/i915/gvt: Support BAR0 8-byte reads/writes
GGTT is in BAR0 with 8 bytes aligned. With a qemu patch (commit:
38d49e8c1523d97d2191190d3f7b4ce7a0ab5aa3), VFIO can use 8-byte reads/
writes to access it.
This patch is to support the 8-byte GGTT reads/writes.
Ideally, we would like to support 8-byte reads/writes for the total BAR0.
But it needs more work for handling 8-byte MMIO reads/writes.
This patch can fix the issue caused by partial updating GGTT entry, during
guest booting up.
v3:
- Use intel_vgpu_get_bar_gpa() stead. (Zhenyu)
- Include all the GGTT checking logic in gtt_entry(). (Zhenyu)
v2:
- Limit to GGTT entry. (Zhenyu)
Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/trace.h')
0 files changed, 0 insertions, 0 deletions