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| author | Andi Shyti <andi.shyti@linux.intel.com> | 2022-12-01 02:58:01 +0300 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2022-12-06 12:52:41 +0300 |
| commit | 09f9b4418e417b6452d1bcd7a9544a68fc1e59d5 (patch) | |
| tree | 6ccdd48748ef6c98bf1adc8f7ea58e74dfe225e9 /drivers/gpu/drm/i915/i915_vma_types.h | |
| parent | f2053d346615f2c6bb4c0663276274b2da3f6871 (diff) | |
| download | linux-09f9b4418e417b6452d1bcd7a9544a68fc1e59d5.tar.xz | |
drm/i915: Limit the display memory alignment to 32 bit instead of 64
The coming commit "drm/i915: Introduce guard pages to i915_vma"
from Chris, was originally changing display_alignment to u32
from u64. The reason is that the display GGTT is and will be
limited o 4GB.
Put it in a separate patch and use "max(...)" instead of
"max_t(64, ...)" when asigning the value. We can safely use max
as we know beforehand that the comparison is between two u32
variables.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221130235805.221010-2-andi.shyti@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_vma_types.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_vma_types.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h index ec0f6c9f57d0..0375812792b9 100644 --- a/drivers/gpu/drm/i915/i915_vma_types.h +++ b/drivers/gpu/drm/i915/i915_vma_types.h @@ -197,7 +197,6 @@ struct i915_vma { struct i915_fence_reg *fence; u64 size; - u64 display_alignment; struct i915_page_sizes page_sizes; /* mmap-offset associated with fencing for this vma */ @@ -205,6 +204,7 @@ struct i915_vma { u32 fence_size; u32 fence_alignment; + u32 display_alignment; /** * Count of the number of times this vma has been opened by different |