diff options
| author | Matthew Auld <matthew.auld@intel.com> | 2023-10-18 15:34:24 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:43:19 +0300 |
| commit | bf6d941c06c9681d0f3d8380e7093d7f79d3eef6 (patch) | |
| tree | 597fda0dcdfbddfaa0cb1493794a6ae4a3db7343 /drivers/gpu/drm/xe/xe_bo.h | |
| parent | 9b49762740e3f2c240877437116635e73718cd47 (diff) | |
| download | linux-bf6d941c06c9681d0f3d8380e7093d7f79d3eef6.tar.xz | |
drm/xe: fix pat[2] programming with 2M/1G pages
Bit 7 in the leaf node is normally programmed with pat[2], however with
2M/1G pages that same bit in the PDE/PDPE also toggles 2M/1G pages. For
2M/1G entries the pat[2] is rather moved to bit 12, which is now free
given that the address must be aligned to 2M or 1G, leaving bit 7 for
toggling 2M/1G pages.
Bspec: 59510, 45038
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_bo.h')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_bo.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h index ba6ffd359ff7..3f4e2818f92c 100644 --- a/drivers/gpu/drm/xe/xe_bo.h +++ b/drivers/gpu/drm/xe/xe_bo.h @@ -50,6 +50,7 @@ #define XELPG_PPGTT_PTE_PAT3 BIT_ULL(62) #define XE2_PPGTT_PTE_PAT4 BIT_ULL(61) +#define XE_PPGTT_PDE_PDPE_PAT2 BIT_ULL(12) #define XE_PPGTT_PTE_PAT2 BIT_ULL(7) #define XE_PPGTT_PTE_PAT1 BIT_ULL(4) #define XE_PPGTT_PTE_PAT0 BIT_ULL(3) |